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Generate continuous random bit stream from noise

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Hi, I am developing a project for Uni at an EEE student which has various stages but I'm struggling with the generation of a random stream of bits from noise which will feed into a shift register. I am attaching the schematic in the hope someone can make some suggestions.

The supply is +6V and -6V
The circuit uses a reverse biased zener 1N4733ATR to generate noise.
This is then amplified by an LM358 Op Amp which I was hoping for around -50mA to +50mA centred at 0.
This goes into a LM393 comparator with a pot to try and centre the output.
Finally I pass it through an IN4148 diode to so that I get either 6V (or 5+ V) or 0V output which goes into the CMOS shift register.

I don’t want to use an MCU.

I'm getting inconsistent results. It seems quite overly sensitive and gives different levels of noise. I'm also not convinced it is random and looking at the output from the op amp on the oscilloscope there may be some oscillation there though I tried to filter out any possible mains interference with RD filter after the amp.

Even if it was complete random I am seeing drift of the centre point and have to tweak the pot so I do get an equal share of 1's and 0's.

This is all quite new to me so please be quite specific about any feedback so I can understand clearly.

Thanks in advance.
 

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What does your output from U3:B look like ?

What is the noise BW you want ?

Note your LM358 has a GBW of 1.2 Mhz typ, so your G = 100 rolls off
around 12 Khz, is that what you want ?

1680735066757.png


The LM358 has a slew rate ~ .3V / uS, that will affect design as well.

Lastly your comparator output is not compatible with a logic input swing
level, which usually precludes no signals below ground.

Possible SR interface :

1680736020797.png


Regards, Dana.
 
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Your technique has a vanishingly small chance of producing a random bit stream.
 

"Generate continuous random bit stream from noise"​


The best solution follows after you define explicit, measurable expectations.
Please defines in terms of : BW, or smallest interval, spectral density ( white noise, pink, brown noise) as AM, FM or PM on a carrier or baseband?
Amplitude dynamic range(binary, 8 bit, 12 bit, 24 bit ?)

Keep in mind any analog signal can be digitized or digital signal converted to analog and include your purpose.

The easiest method to generate a random bitstream is a PRSG pseudo-random sequence generator using XOR gates and a maximal length sequence from SIPO register of any length. 2^n-1 at any clock rate.

You should know there are books written about noise generators, entropy and measurable characteristics.
 
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Here are some resources you might want to familiarize yourself with.
 
1. The LM358 has a relatively low gain-bandwidth product. Its maximum open loop gain decreases with increasing signal frequency. Basically, for any particular closed loop gain in a circuit, the response is flat up to the point when you intersect the open loop frequency response curve, at which the amp acts like a single-pole lowpass filter. For a gain of 100, this happens at around 5 kHz. So while the zener noise might be very wide band, the output amplitude of U3B will roll of starting at around 5 kHz when observed with a spectrum analyzer This will have the effect of reducing the high-frequency content of the noise going into the comparator. Out of the comparator, the number of narrow pulses will be disproportionately lower than the number of wide pulses.

2. Try the circuit with no hysteresis around the comparator. Hysteresis removes transitions due to low amplitude parts of the noise signal, another way of low-pass filtering the result. Delete R4, R5, R8, and RV1, and tie the pin 3 comparator into to GND.

3. C1 and C2 both ae high-pass filters, which will affect the low-frequency corner of the noise spectrum.

You don't say what type of noise bandwidth you want, and that is important. Do you really want the clock or data input signal frequency to vary from Hz to kHz? Or hundreds of kHz with faster parts? What is it you are trying to achieve?

ak
 
Here are some book recommendations on noise generators, entropy, and measurable characteristics:
  1. "Noise and Fluctuations: An Introduction" by L. Mandel and E. Wolf - This book covers the basic concepts and principles of noise and fluctuations, including discussions on entropy, noise generators, and their measurable characteristics.
  2. "Noise Reduction Techniques in Electronic Systems" by H. W. Ott - This book provides an overview of different noise reduction techniques and covers topics such as sources of noise, measurements of noise, and noise modelling.
  3. "Introduction to Random Signals and Noise" by W. L. Ligon III - This book covers the fundamentals of random signals and noise, including topics such as entropy, probability distributions, and random processes.
  4. "Information Theory, Inference, and Learning Algorithms" by David J. C. MacKay - This book covers a wide range of topics in information theory, including entropy, noise, and channel capacity. It also includes discussions on coding theory and machine learning.
  5. "An Introduction to Information Theory: Symbols, Signals and Noise" by John R. Pierce - This book covers the basics of information theory, including discussions on entropy, noise, and the Shannon theory of communication.
  6. "Random Processes for Engineers" by Bruce Hajek - This book provides an introduction to random processes and covers topics such as probability, statistics, entropy, and noise.
These books should provide a solid foundation for understanding noise generators, entropy, and measurable characteristics.
 
Your technique has a vanishingly small chance of producing a random bit stream.
The interface shown in post #3 is just to translate the -6 to +6 from the OpAmp
used to amp the zener noise in OP circuit, to a logic level unipolar signal.

Regards, Dana.
 
Thank you for the overwhelming and prompt response everybody! There is a lot to work through there but to clarify a few points around the specification required:

I chose to use avalanche noise from the zener and would ideally like to continue down that route.
I'm not looking to study the theory of noise as it would be beyond me, and the time that I have. Thank you Tony for your suggested reading.

I am trying to keep the components to simply well known rather than specialist chips or ADC convertors etc.

The goal is turn the analog noise into a streams of 0's and 1's that go into a shift register. The frequency is less critical other than to say I had decided on around 1kHz. The output of the comparator is going into a CD4015B shift register.

I need to generate at least 8 random bits. I will use a NE556 as a pulse extender so that when it is triggered, it will clock the shift register for perhaps 200ms meaning more than enough random bits have been shifted into the CD4015B.

Therefore the frequency can be low, but not such that a human would know there was a delay. The frequency shouldn't vary but it is less critical in what I am trying to achieve in this way.

The bandwidth of noise. I haven't been specific and perhaps that is something I need to try and understand better but I did try to adjust the filter to cut out AC as I was seeing this on the scope.

Ideally I would like to try and improve the circuit that I have using zener noise, amplification and a comparator rather than take a new approach and it will clearly help my understanding grow.

Dana, ak I will work through your suggestions now and see what I can understand.
 
Another approach, use a SOC (single chip) to gen the sequence and move into a SR
for further work. Again a single chip. The PRS_1 gens the noise.

1680773510126.png


There are 2 SR's shown to capture noise sequence, the 32 bit which you can use DMA
to other logic/peripherals, or the 64 bit (one would mod the 64 bit Verilog code to
create 32 bit version) to perform serial to parallel out to pins. This is one of many
features on chip, you can create your own HW components with schematic capture
and/or Verilog.

Other stuff on this SOC are (multiple copies of each in many instances) :

1680773236323.png


IDE (PSOC Creator) and compiler free. Rich library for each resource of f() calls to manipulate components.
A "component" in PSOC land is an onchip resource as shown above.


Regards, Dana.
 
I know you stated no micro but when I've needed a (hopefully) random number in the past, I've read the ADC and just used the bottom bit. The rest of it might have a bias but the bottom bit is pretty random.

Note, random does not mean equal ones and zeros, just balanced over time.

Mike.
Stat quote, you (well most) have more arms and legs than the average person. And, my favourite, shark attacks directly correlate with the sale of ice cream. STOP selling ice cream NOW.
 
Note on post # 13, you don't have to use the micro in it, just all the routable
logic capability and analog stuff, and as you mention you are feeding noise
into a SR, and I 'will take a giant leap here and assume the SR is used with
other components ?

So take your zener, use one of the OpAmps in the SOC, and one of the
comparators in SOC (if you do not want to use the digital generation
approach) and feed that to SR and .......ALL ONE CHIP.........with plenty
of other stuff available for the total design.

Note on Zener approach, apparently their noise performance varies widely
device to device, so selected/screened in real applications. If this is a one off,
no need for concern, otherwise a consideration to go digital which suffers no
such considerations.

Given that you are using noise as input to SR, I assume you have a separate clock
source to clock the SR. That means the randomness of the bits is not so random,
and will have a strong correlated component of the clock source in the bits pro-
duced. Just a thought..


Regards, Dana.
 
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Just for the heck of it I am going to try this approach -

1680782485182.png


I am using onchip DAC to look at result with spectrum analyzer. Note since this is single supply
the OpAmp and Comparator biased up internally with the Vdd/2 Vref.


Regards, Dana
 
Thanks Dana. A random stream of 0's and 1's, coupled with a random burst capture to fill the SR should mean I get an 8 bit random word good enough for the next stages. The AD chip looks good but is outside of the constraints of this project. This isn't a commercial application in any way so repeatability is not so important.
 
Here is a first cut of post #16 results. Video attached.

I have persistence turned on in scope so I can see that all DAC values are present
in noise output, blue trace.

Yellow trace sig out of Noise Gen OpAmp, method analog devices used amping up its
intrinsic noise.

You refer to A/D chip, what A/D chip ?

Regards, Dana.
 

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Thank you Dana, I mean onchip DAC, I am not clear on what you are doing there Dana, but as I said, I would like to solved it using the components I have listed or similar.
 
The DAC was just to regurgitate the captured random # in SR and monitor it,
show that in analog domain the OpAmp noise gen was working to produce
all possible 8 bit values captured in SR. For testing only.

Basically think we gened the noise, then converted to a digital value,
then back again into noise. As verification.

What are you going to do with the SR value, what's the purpose of the the SR
for rest of system ?


Regards, Dana.
 
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