Verilog:full adder and shifting concept

Hi all,

Im new to this forum and currently need to find some information regarding the concept of full adder and shifting method when designing using Verilog HDL.
Can you help to give me to get some understanding about above statement or at least pull me some example in verilog files that i can add in to my do-it-yourself activites.
I have the basic understanding the Verilog HDL code and currently using Quartus II as designing software.
Hope you can share me some information.

Thanks,
photoelectric

"Some information" is too vague to try to respond to. Please try to be more specific about what information you need.

try these;
fpga4fun.com - HDL tutorials
https://ece.wpi.edu/~wrm/Courses/EE3810/geninfo/Welcome%20to%20the%20VHDL%20Language.pdf
VHDL-Online Main Frame
you should find what you need.