Gee, just wanted to clarify your statement :
There's no voltage divider since the pulldown is on the "input" side of the series resistor.
And we are not talking about pulldown value, eg. if logic driver is ever
in tristate and we are concerned with power MOSFET gate leakage turning
itself on, so we have to use lower pulldown, more V divider effect. Another
.05V of lost gate drive.....OMG. Or stray pickup impact of a high Z node.....
so many worries, so little time.
Not to forget for ultra low power design, low cost, we, the industry, use small I/O
device sizes where ever possible (FPGA) = high Rdson = GADS N x .05V which can
be huge......
So complicated we need specialists to make these decisions.
How long you been using those sloppy 0.1% components ? [end sarcasm mode]
Regards, Dana.