• Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.


Not open for further replies.


New Member
hi, i am a student at WKC in my final year and am currently just finishing off my final project. i have built a fairly basic reaction timer that counts up in tenths of a second. i have used a mixture of CMOS and TTL chips in my circuit. not a good idea ,i know, but my circuit seems to work fairly well. will there be any long term deffects because of this?


The noise margin will be affected at the interface between ttl and cmos, if not properly accounted for. So, the unit may fail intermittently, but there shouldn't be any long term effects or degrading.


Well-Known Member
Most Helpful Member
The TTL high output level is not a full logic "1" for the CMOS. Thus the CMOS may draw more current then normal as the input PMOS transistor may not be fully off as it should be with a logic "1". (See Logic Voltage Thresholds for TTL, CMOS, LVCMOS, and GTLP IC's for a comparison of the logic threshold levels.) To avoid this you should have a pull-resistor (10kΩ or so) to +5V on all TTL outputs connected to a CMOS input.


New Member
The main thing when using CMOS is to be sure to tie unused input pins high or lower, never floating free. This applies even to unused gates in multi-gate packages. With TTL you could get away with unwired inputs floating high, even though it's not a recommended practice, however with CMOS it would cause gate oscillation and over dissipation of the package.

Not open for further replies.

Latest threads

EE World Online Articles