Trouble with 74HC163 Synchronous Counter - Advice needed.

[archery_tim]

Hi there,

I hope you can help, I am trying to build a basic synchronous counter with a74HC163 device. I have attached the basic circuit diagram, however ENP ENT LOAD CLR are all tied directly to vcc. A-D are tied directly to ground. Outputs Qa-Qd are simply driving logic gates. RCO is not connected. The Clock comes from a momentary switch and is fully debounced and looks perfect in a storage scope.

After construction, the outputs of the counter seem unpredicatable and, most of the time they do not latch, Qa (LSB) simply follows the clock pulse and returns to Zero. At times they seem to latch on the negative going pulse also When looking closer with an scope, there seems to be a short spike on the negative rail during the negative going clock pulse.

Should i be using pull-up resisitors for the connections to the chip instead of connecting directly to VCC?

Im sure im going something obvious wrong, but i cant seem to figure it out. I have rebuilt the circuit three times, and each time i have exactly the same trouble. I have also replaced the chip too with the same result.

Can anyone suggest where i may be going wrong - this is such a simple circuit and its embarassing that i cant seem to get it operational

I would really appreciate any help
Best regards
Tim

 

[Diver300]

Please post a circuit large enough that the pin functions are readable.

Do you have decoupling capacitors on the power lines?

 

[Mikebits]

Can you tie the load pin high? I thought you needed that to load the counter.

 

[Diver300]

I can't see anything wrong with the circuit. However, the fact that something is happening on the negative going clock pulse, and the spike on the negative rail would tell me that the layout and grounding are poor.

Can you show us the debounce circuit?

 

[archery_tim]

Thanks for the responses.

I attach a larger more readable version of the circuit. Also let me clarify a few questions & points:

1) Yes the chips are decoupled - originally they were not, and the output never latched. Once they were inserted, the output latches sometimes.

2) I appologise - i am seeing the short spike on VCC not ground. (measuring at the CLR pin)

3) The switch debounce circuit (cap+resistor) feeds a 555 with logic to generate a clean input clock pulse that aways the same length (800ms)

I have buzzed through the supply lines and checked connections, and both are 4-5 ohms to the regulator. The supply is a simple 1A +5v regulator - driven from a +12v lab supply (although i have operated this without the regulator - directly form the supply - same result)
The current draw when on (for the entire circuit - pretty big) is about 30mA

This might seem an erroneous peice of information, but i constructed the same circuit using J-K flip flops and i ALSO got a similar non-latching of the output - What on earth am i doing wrong, its driving me crazy. The only common element is the PSU - and that is a decent Lab supply. *normally* i seem to know what im doing

Thanks in advance.
Tim

 

[ericgibbs]

tim,
Disconnect the Clear from the other pins to +V.

Connect Clear via a 4K7 to +V and to 0V via a 0.1uF cap.

On power up this should Clear the LS163 by providing a reset pulse.

Lets know what you find.

 

[archery_tim]

tim,
Disconnect the Clear from the other pins to +V.

Connect Clear via a 4K7 to +V and to 0V via a 0.1uF cap.

On power up this should Clear the LS163 by providing a reset pulse.

Lets know what you find.

Thanks, for this. Unfortunatly been there - done that . I originally implemented a power-on reset, but when i started having trouble, i connected manually to +V and this didnt have any effect on the response. A manual reset during operation does reset - but doesnt 'fix' the faulty operation

Any other ideas?

Thanks again

 

[Roff]

The 555 creates a big current spike each time it switches. You need 10uF and 100nF caps in parallel, with short leads, connected to vcc and ground, as close to the 555 as possible.