Tremolo control - input signal seems to be riding the output

LTSPICE - .asc file, model and sub attached.

In this basic tremolo control, I cannot avoid what seems to be the input signal riding the output.

As is, even if the JFet is cut (??) I still get the equivalent of the input signal, at the output.

Sure it is more than 100% modulation; done on purpose to put in evidence that the JFet is cut.

Around this for many hours, I supose I am wrongly biasing the opamp but cannot see where or how.

Comments will be appreciated.

What exactly do you want the output to look like?

As the FET is configured the U2 op amp gain can vary from 1 (follower) to about 6.3 with the FET going from off to full conduction.
It doesn't sound like that's what you wanted.

Edit: If you want the output to go full-off then add a 10kΩ resistor in series with the + input to U2 and connect the drain of J1 to the junction of that resistor and the + input.
Connect R5 to Vref.

crutschow said:

What exactly do you want the output to look like?

As the FET is configured the U2 op amp gain can vary from 1 (follower) to about 6.3 with the FET going from off to full conduction.
It doesn't sound like that's what you wanted.

Edit: If you want the output to go full-off then add a 10kΩ resistor in series with the + input to U2 and connect the drain of J1 to the junction of that resistor and the + input.
Connect R5 to Vref.

Click to expand...

My bad; at a certain point is a voltage follower. Yes!

I want the output following the modulation imposed by the signal at the gate, as you say, output full-off.

Not sure I understand your proposed changes (much less why). I will try to work it out.

Gracias Carl!

/Edit to add:

No time yet to play with LTSpice but what you are suggesting is to stop messing with the gain setting and implementing an attenuator for the input. Am I right?

Edit/

atferrari said:

My bad; at a certain point is a voltage follower. Yes!

I want the output following the modulation imposed by the signal at the gate, as you say, output full-off.

Not sure I understand your proposed changes (much less why). I will try to work it out.

Click to expand...

Having an output gain of one as stated in your first sentence doesn't seem compatible with your second requirement of the "output full-off".

My change in the circuit was to allow reducing the signal gain to zero to get that full-off.