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Stupid question / Decade Counter

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Space Varmint

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Is the Qd output the divide by 10 frequency? I have used decade counters using the "carry output" but I don't have one hooked up right now. If I remember correctly it is an asynchronous signal. Would it be suitable to run into another decade counter and get valid divide by ten BCD on all Q outputs if I run Qd from one into the clock of another?
 
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BrownOut

Banned
Post the part number of the part you're using, and any data you have on it.
 

BrownOut

Banned
It appears, from looking at the datasheet, that indeed Q4 is a divide by 10 output, when the chip is configured for a decade counter. I don't know what that other configuration is. Look at fig. 6 timing chart ( top portion -- decade counter ) Q4 is clearly high once every 10 cycles, although it's high for two cycles.
 

BrownOut

Banned
Well those pins are not on the pinout. There are QA-QD and NOT clockA and NOT clockB. For decade counter config, NOT clock B is connected to QA
 
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Mikebits

Well-Known Member
Is the Qd output the divide by 10 frequency? I have used decade counters using the "carry output" but I don't have one hooked up right now. If I remember correctly it is an asynchronous signal. Would it be suitable to run into another decade counter and get valid divide by ten BCD on all Q outputs if I run Qd from one into the clock of another?
The async nature only has to do with reset. I would not recommend using the q outputs as a clock. These counters Q outputs are often glitchy when switching states which would cause the follow on stage to miscount. I would use common clock for all counters.
 

Space Varmint

New Member
Well those pins are not on the pinout. There are QA-QD and NOT clockA and NOT clockB. For decade counter config, NOT clock B is connected to QA
Sorry your right. I was looking at some schematics. I know what they are saying.

Q0 would be Qa. Did you derive that from the data sheet? That sounds the same.
 

Mikebits

Well-Known Member
One more thing. It was not a stupid question :)
 

Dean Huster

Well-Known Member
"Asychronous" with a counter means the same as "ripple" as opposed to "synchronous". All outputs and reset/preload inputs of a ripple counter are asynchronous, that it, they are not synchronized with the clock input.

You're maybe confusing this with the term "symmetrical". The Qd output of most any counter that is not a pure binary counter is often non-symmetrical, that is, the output is not a perfect square wave.

The 7490 TTL counter is such a beast. However, if you don't use the outputs to drive a display, you can switch the divide-by-2 section with the divide-by-five section so that the divide-by-two section is last in each decade chain and then you WILL have a symmetrical output. But the larger counter chips that incorporate several 7490-like stages do not have access to the divide-by-two stages so you can't do that.
 
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BrownOut

Banned
Ah! So that's the purpose of the "other" mode. But if the OP is only interested in clocking a subsequent stage, symmetrical output isn't required. Thanks for that description.
 

Space Varmint

New Member
Ah! So that's the purpose of the "other" mode. But if the OP is only interested in clocking a subsequent stage, symmetrical output isn't required. Thanks for that description.
Actually I was concerned somewhat with ripple carry like the '191 that has the RCO output used to synchronize successive stages. I figured with them being "not symetrical" as you put it (which is a good point), I might be running into some really sloppy tolerance. Still, I am most impressed BrownOut how you derived that from the data sheet. Did you use the logic diagram?
 

Dean Huster

Well-Known Member
You do have to be careful with counters. If they're ripple counters, they'll ripple in cascade. And just because a counter is a synchronous counter doesn't mean that it's synchronous in every sense or will be synchronous in cascade.

For instance, the 74192 synchronous decade counter is synchronous in its counting only. Parallel load and reset are asynchronous operations. And when you want to cascade them, the various stages will be rippled even though within each stage it's synchronous. You have to use a 74160-series counter to get full synchronous operation in all phases.

But you'll still potentially have a non-symmetrical Qd output if it's not a straight binary counter. As mentioned, it takes a pretty special application of a counter such that you require a symmetrical Qd output. Using a Qd output as the gate input for a frequency counter would be a bad idea!
 

Space Varmint

New Member
You do have to be careful with counters. If they're ripple counters, they'll ripple in cascade. And just because a counter is a synchronous counter doesn't mean that it's synchronous in every sense or will be synchronous in cascade.

For instance, the 74192 synchronous decade counter is synchronous in its counting only. Parallel load and reset are asynchronous operations. And when you want to cascade them, the various stages will be rippled even though within each stage it's synchronous. You have to use a 74160-series counter to get full synchronous operation in all phases.

But you'll still potentially have a non-symmetrical Qd output if it's not a straight binary counter. As mentioned, it takes a pretty special application of a counter such that you require a symmetrical Qd output. Using a Qd output as the gate input for a frequency counter would be a bad idea!
I actually built a freq counter using the '160s years back and it does work quite well though I realize there is no output to compensate for the ripple. I think they are pretty much out dated????? I have high hopes for the '390 because I think that odd "Qa to clock2" arrangement is used as a ripple adjust and possible master reset. I suppose at this point I just need to get them in my hot little hand & see :D. Normally I would opt for a processor counting formula but cost & time constraints don't allow. So this is really a quick & dirty arrangement but I don't like slop.

But mr BrownOut. If you are around, I am interested in how you derived that configuration from the data sheet. I came up with it by looking at other peoples designs. I figured they used trial and error or word of mouth...lol.
 
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Space Varmint

New Member
Hey Dean Huster. I noticed your signature. That's quite impressive! That wasn't a billed response was it? ;) Hey, but thanks for reply.
 
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