ProFPGA
Banned
hi all,
i have programmed a 16f84a with simple routine to light up three leds on RA2,3 and 4, with a delay of 2.50sec ( with a 4mhz cystal ). it programmed well .
I have also tied MCLR to pull-high resistor .
but it doesnt run , only when i pull the vcc wire out of bread brd and touch it again the LEDS blink and turn off.
here's the code :
list p=16F84A
;Specifying SFRs
status equ 03
porta equ 05
trisa equ 05
portb equ 06
trisb equ 06
delcntr1 equ 11
delcntr2 equ 12
org 00
;Initialise
start bsf status,5 ;select bank 1
movlw B'11111111'
movwf trisb ;portb bits 0-7 input
movlw B'00000'
movwf trisa ;porta bits all outnput
bcf status,5 ;select bank 0
clrf porta
loop movlw B'00010000'
movwf porta
call delay
call delay
movlw B'00001000'
movwf porta
call delay
call delay
movlw B'00000100'
movwf porta
call delay
call delay
goto loop
;Introduces delay of 1.25sec approx, for 1 MHz clock
delay movlw D'250'
movwf delcntr2
outr movlw D'250'
movwf delcntr1
innr nop ;10 inst cycles in this loop
nop
nop
nop
nop
nop
nop
nop
nop
nop
decfsz delcntr1,1
goto innr
nop ;10 inst cycles in this loop
nop
nop
nop
nop
nop
nop
nop
nop
nop
decfsz delcntr2,1
goto outr
return
;-----------------------
end
any clues ????
i have programmed a 16f84a with simple routine to light up three leds on RA2,3 and 4, with a delay of 2.50sec ( with a 4mhz cystal ). it programmed well .
I have also tied MCLR to pull-high resistor .
but it doesnt run , only when i pull the vcc wire out of bread brd and touch it again the LEDS blink and turn off.
here's the code :
list p=16F84A
;Specifying SFRs
status equ 03
porta equ 05
trisa equ 05
portb equ 06
trisb equ 06
delcntr1 equ 11
delcntr2 equ 12
org 00
;Initialise
start bsf status,5 ;select bank 1
movlw B'11111111'
movwf trisb ;portb bits 0-7 input
movlw B'00000'
movwf trisa ;porta bits all outnput
bcf status,5 ;select bank 0
clrf porta
loop movlw B'00010000'
movwf porta
call delay
call delay
movlw B'00001000'
movwf porta
call delay
call delay
movlw B'00000100'
movwf porta
call delay
call delay
goto loop
;Introduces delay of 1.25sec approx, for 1 MHz clock
delay movlw D'250'
movwf delcntr2
outr movlw D'250'
movwf delcntr1
innr nop ;10 inst cycles in this loop
nop
nop
nop
nop
nop
nop
nop
nop
nop
decfsz delcntr1,1
goto innr
nop ;10 inst cycles in this loop
nop
nop
nop
nop
nop
nop
nop
nop
nop
decfsz delcntr2,1
goto outr
return
;-----------------------
end
any clues ????