• Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

SMPS / MOSFET amp FET dead time questions

Not open for further replies.
OK, it;s not actually a SMPS, but similar, a 136kW LF amp. I built it some time ago.

Having suffered with blown FET's on a 1kW 136khz Class D amplifier since doing some circuit mods I realized the limitations of my novice status and did some Googling. I had been looking at gate and drain wave forms and saw nothing horrible to my eyes. I then read up on "dead time" the time neither device should be on to stop short circuits or over current, using two channels and two probes. This gives the waveform attached (I hope...) and to me there doesn't seem to be any real dead time. Is it my measurement inabilities, my misunderstanding of dead time concepts, or have I found an issue? The amp usually uses two paralleled FET's per "side", to minimize cost in blown FET's I have been running just one per side. Even on reduced voltage to the PA FET's I get one popping quite often, and I can see no other issues, like bad antenna matching etcetera.

Where does "dead time" come from? Is it from the architecture of the driver chips(s) itself / themselves? Or is external circuitry needed? I see propagation delay figures cited, but I don't think this is the same as dead time. The fact I see no dead time figures stated for either of these IC's makes me wonder how it is created...

I put the red and blue cursors on where I expected to see the dead time, but the switching looks instant, maybe I am not running the scope fast enough? On the drain waveform capture I am not sure what the blip is before the drain voltage rises. Is that some dead time, or an attempt for both devices to conduct together?

I changed from a single dual output inverting gate driver chip type TC4426 to two single output inverting chips type TC4452 in order to be able to drive more powerful, higher gate capacitance MOSFET's in the future. Maybe these have caused an issue, I had nothing like the same failure rate before my mods.

I attach links to their data sheets and the amp's schematic. Thanks.

Basic schematic showing original single, dual output driver IC, which seemed to be far kinder on FET's


Gate driver signal capture at gates of the PA FET's, just running a pair at 50V:


Drain pins captures:


Original dual output driver IC specs:


New dual driver chips, each with just a single output, much higher current and gate capacitance ability:


Thanks for looking!


Well-Known Member
Most Helpful Member
Neither of those driver chips inherently provides dead time for the driven FETs. Some external arrangement would be needed. The CD4013 in your amp circuit does not provide it.


Active Member
As Alec says, there's nothing providing an explicit dead time in this circuit. The dead time doesn't need to be much - as far as I can see it just needs to be long enough to ensure that one FET has definitely turned off before the second one starts to conduct.
I don't know enough about your application to know what effect "too much" dead time would have, but the obvious way (to me) to approach this would be to add plenty of dead time and see if it stops blowing transistors - at that point, at least you know where your problem lies and you can start bringing the dead time back down until you get your desired performance.
The easiest way of adding a little dead time is to bypass the gate-stopper resistor with a diode (anode towards the gate) to that the FET can turn off quickly though the diode, but takes a little longer to turn on as the gate has to charge through the resistor. This obviously gives you a slightly slower turn-on and thus higher switching losses (you might have to go for a bigger gate resistor in order to get an appreciable difference in turn-on and turn-off times).

Your gate drive waveforms look a bit "ringy" - improving this may help, but there are others here who can probably give better advice as to how (I imaging upping the gate-stopper resistor would be a start). I don't quite understand what's going on with the drain waveforms either - it might be interesting to see a plot of a gate and drain on the same time axis.


Well-Known Member
Most Helpful Member
I have used 25 to 50nS for low voltage high speed MOSFETs when the gate drive current is high.
On 500 volt MOSFETs I often use 100 to 200nS.

You could look at "L6384E" from ST Micro.


Well-Known Member
Most Helpful Member
Hi CW,

Inverters are great fun- I have built many. They are also great for blowing up power transistors- I have blown up many.:)

As you know doubt know the reason for the fatalities are:

(1) Over voltage
(2) Over current
(3) Too higher current change DI/DT
(4) Too higher Voltage change DV/DT
(5) Over temperature
(6) Going outside the safe operating area (SOA)

Inverters are pretty good at causing all of these fatal conditions.

The drain waveforms that you posted @ http://www.gatesgarth.com/drain-no-dead-time3.jpg shows, as you suspected, that both NMOSFETs are conducting at the same time: the fast negative going edge on the drains indicate when the MOSFETS conduct current.

This is a more hazardous than it may at first seem because, not only are the two NMOSFETs fighting one another, but they also cause excess current to flow through the transformer winding which will most probably force the core into saturation with the result that even more current will flow.

Finally the MOSFETs simply cannot supply the current demanded and their collector voltages rise. You can see this affect by the small voltage blips on the image.

As this continues the MOSFETs get hotter and the core gets hotter so the problem gets worse because the core saturates at less current and the NMOSFETs current capability is reduced.

There is usually another problem which is not apparent on your image, but might still be there, and that is voltage overshoot which takes the form of fast high voltage spikes.

All of the above are disastrous for the transformer and the NMOSFETs.


Not open for further replies.

Latest threads

EE World Online Articles