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Simulation problem

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Dr.EM

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Hi, I made the below circuit on circuit maker 6 student. I just wanted to see whether it would work, but every time I went to run, it reoprted conversions at node 22 or something. Anyhow, i'll explain what the idea is. There are 2 oscs here made from 555 astables, running at different frequencies. This circuit is designed to "hard sync" them. This means that every time the first one goes high, it forces the slave one to begin a new timing cycle. The second osc will run normally if the sync input is low. I have used a 2 input OR gate, so that the slave oscillator will trigger itself, acting as an oscillator, but also the other oscillator can trigger it. Is this making sense, it kind of goes round in circles, sorry. Anyhow, could anyone tell me if there are errors in the circuit, or whether its just the program not coping (i've had circuits that don't simulate but do actually work). The circuit is designed for audio use, as part of a synth btw, to create unusual waveforms.
 

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U2 won't oscillate with its reset pin at 0V.
 
I would put a 1 meg Pullup Resistor on the Trigger of U1 and a Cap between U3A output and that trigger.
 
Hmm, think i'll just have to make this for real when I can. The resistor and capacitor are a good idea though, to prevent false triggering and to block DC respectively I assume? Pullup means it connects to +V, not ground?
 
Dr.EM said:
Hmm, think i'll just have to make this for real when I can. The resistor and capacitor are a good idea though, to prevent false triggering and to block DC respectively I assume? Pullup means it connects to +V, not ground?

Get your sim problem fixed yet? I would suggest using a ".IC" inital condition on one of the oscillating nodes. Sometimes, sim software needs this to get the circuit started.
 
i just tried sometime using a 555 and combined it with logic gates in circuit maker. the program did not work.
 
Ah, so this sort of thing often happens? Anyone have any reason for why it might not work in real life?

Not entirely sure what you mean by IC on one of the nodes, but it does come up with some jargon about node 23 covergence :?
 
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