Perhaps something like this? I've only shown one pass transistor plus its current-limiting add-ons. Pretend the regulator U1 is a 317. Ignore resistor 'Reg' which is just for the simulation so that regulator current can be monitored.
The graphs show currents and output voltage for loads between 0.01Ω and 10Ω.
When Q1 collector current tries to rise above ~3A the voltage drop across R1 turns on Q2, raising Q3 base voltage and so reducing Q1 base current flowing through Q2 and R3, thus clamping Q1 collector current at ~3A.