I am trying to design a serial-in parallel-out shift register for my 4-bit DAC. I tried simulating the following circuit but only the first few bits(serial in:01011)are shifting and the rest bits are disappearing. Am I missing something here?
Could someone please let me know what's wrong with it. It would be really helpful.
Thank you
It looks like there's something wrong with the first flipflop as d3 is wrong. Once d3 changes the change ripples through as it should. Double check the first flipflop.
I take it that this is a simulator of some kind rather than real hardware.
The problem could be due to the relative timing of the clock pulses and the input data.
I suggest that you make the clock pulses narrower, say half the width that they are now, and, delay them slightly so that the clock edges do not correspond exactly with the data edges.