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Schmitt Trigger in VHDL?

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Snowman

New Member
Hi,

I'm building a circuit that requires a large number sensors - simple photodiode and resistor pairs (chosen for their extremely low price) piped to a 7414. These sensors work great on the breadboard but in order to prototype an entire circuit with 150+ of these sensors, I would need 25+ 7414 chips.

In order to handle these sensors, I've decided to use a CPLD and I was wondering if there is anyway to simulate a schmitt trigger using VHDL. Please keep in mind I'm totally new to VHDL (I do program fluently in several other languages though so have no problem understanding programming concepts).

Thanks in advance!
Avital
 

Roff

Well-Known Member
Snowman, have you done a Google search for "vhdl schmitt"?
BTW, your name doesn't mean you're a coke-crazed lunatic, does it? If so, I'd sure hate to piss you off! :lol:
 

Snowman

New Member
I always do a web search before posting any questions. I've tried different combinations of vhdl and schmitt trigger. I can't find anything related excepted unanswered newsgroup questions similiar to mine. I was wondering if someone had personal experience/had written vhdl code to achieve this.

And, no, my name has nothing to do with any drugs :) I live in Toronto, Canada...it's cold up here and I the calendar in front of me had a pic of a snowman so :)
 

Roff

Well-Known Member
I took a class in VHDL once, but never used it, so you know what that means...
The first two hits on a Google search for "vhdl schmitt" look relevant to me. Maybe you can tell me what's missing.

Ron
 

laroche73

New Member
schmitt trigger

One problem with "rolling your own" schmitt trigger in a CPLD or FPGA is that it requires feedback external to the device (you can't do it internally).

Here's an old Xilinx app note to illustrate: https://www.xilinx.com/xcell/xl19/xl19-34.pdf

Each schmitt trigger requires an additional CPLD pin and two resistors. They also have a lower imput impedance than a CMOS version like the 74HC14, which may not be a good match for your photodiodes.

Here's a listing of standard logic schmitt triggers. Unfortunately, an octal package is probably the best you'll find, and they're harder to get than the 74HC14s.

https://www.semiconductors.philips.com/catalog/219/282/27063/29503/index.html#29503
 

Roff

Well-Known Member
As I said, I'm basically in over my head here, but Xilinx CoolRunner II appears to have optional Schmitt-per-pin inputs. I have no idea whether there's a part in that family that is suitable for Snowman, or if they are even available. I found it by Googling "cpld schmitt".
 

laroche73

New Member
Coolrunner

You're right! That's a first for PLDs as far as I know. I've never used the CoolRunner parts, but it always looked like one of the better CPLD architectures to me, consuming far less power than competing CPLDs. Xilinx acquired the line from Philips back when they were trying to break into the PLD market (about the same time Altera was trying to get into FPGAs). They've obviously made some nice improvements. I thought Xilinx was discontinuing some of the CoolRunner parts, not sure about which ones. They offer a $49.95 kit on their website to get started.

This app note has more info:

https://direct.xilinx.com/bvdocs/appnotes/xapp378.pdf
 

Snowman

New Member
Unfortunately, using CoolRunner isn't an option for me as I have already commited to 9500 series CPLDs. Moreover, as laroche pointed out, CoolRunner's present/future is uncertain. However, I found the link regarding modifying the hystersis very useful. I did not know that all inputs already had 100-200mV of hystersis.

I will have to experiment once my shipment of CPLDs arrives to see if this is enough for the output my sensors yield. Otherwise, I will try to add external resistors as outlined by the document. Basically the schmitt trigger equiv is not possible in VHDL - this is what I've gathered.

Also, I looked at the link for the octal schmitt trigger - this does seem to be the largest package out there (I wasn't even able to find this, I was using the hex so far). I guess this isn't so bad, I may end up using the 20 octal schmitt trigger chips external to the CPLDs. I reckon the 20 chips will not draw too much current - anywhere from 20mA to 200mA, depending on CMOS/TTL. Inelegant but may be a simple "necessary evil" in order for me to create my prototype.


I will have my CPLDs within a week, so I shall have to test then - I'll post again to let you know how it went.


Thanks very much for your advice again, very much appreciated!!!
You guys are awesome! :)
Avital
 

laroche73

New Member
schmitt trigger inputs

Hi, Snowman, sounds like you have an interesting project on your hands :) . Just a few thoughts about VHDL in general. What can be synthesized in VHDL is a subset of what can be simulated, and depends on what the CPLD hardware is capable of. Being able to work at a higher level of abstraction is great, but it's still important to understand the underlying CPLD architecture if you want to make good use of it. You can instantiate a schmitt trigger on the CoolRunner II parts, only because it's built in to the hardware. The app note illustrates why you can't construct a schmitt trigger with a 9500, it's not possible to synthesize a resistor inside the part (however, you can connect the buffers together in VHDL, and add the resistors externally).

Keep in mind that the app note was written in '93, when the only Xilinx parts in existence were the XC2K,3K, and some 4K parts. I'm not sure the comment about input hysteresis applies to the 9500 series, you may need to run a simple test to find out.

You might have trouble finding a source for the octal schmitt-trigger parts. If you go with external schmitt triggers, stick with the 'HC series; the input impedance is much higher than 'LS (or any you make using the app note method), and most of the power dissipation will probably be associated with input current (assuming the photodiode outputs don't swing from rail to rail).

Good luck with it!
 

Snowman

New Member
Yes, I didn't think it would be this hard when I first started the project!
I don't know why I don't think of such obvious answers as searching on the Xilinx website - overthinking I suppose :) I did a search on their site after you posted that app note and found this:

https://toolbox.xilinx.com/docsan/xilinx6/books/docs/cgd/cgd.pdf

On P. 737, there is a chart of chip architecture vs. Schmitt trigger support - the *only* one with support is-as was mentioned before but just so we can all be sure now-the CoolRunner II. Since I have already commited to the 9500 I suppose I will have to experiment, as you say. Regarding the CPLD internal arch - I thought there may be a higher level method (ie: VHDL) to utilise the latches and clock to form a rudimentry schmitt trigger/monostable - as I recall sometimes using those as switch debouncer circuits. I will shifting away from TTL to CMOS as recommended. I'm sure I'll be posting more questions when I actually get the hardware to play with...

Thanks again! :)
Avital
 
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