RS-485 (MAX487 / MAX485) - On-chip fail-safe feature

[esm.]

Hello all.

I have a good knowledge on RS-485 buses. I have some doubts about the internal fail-safe feature of MAX487.

I know how to do a fail-safe biasing using external pull-up and pull-down resistors, but my doubt is just about the internal fail-safe feature of these transceivers.

Currently I can't do tests in practice with my ICs (MAX487). I won't use a MAX485 because I could need more than 32 nodes attached to the RS485 bus (MAX487 supports up to 128 nodes).

When receiving at the RS485 bus, I know that:
VA-VB >= 200mV ---> RO pin is level '1'
VA-VB <= 200mV ---> RO pin is level '0'
VA-VB > 200mV && < 200mV ---> RO pin has undeterminated logic state


MAX487 / MAX485 datasheet says: The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.


Considering the following condition:

1) Supply voltage = 5V
2) DE and RE pins at level '0' constantly (that means transmit is disabled and receive is enabled)
3) A and B pins left floating (No termination resistor and no fail-safe biasing external resistors connected). Nothing connected to both pins A and B

Questions

1) Does these RS485 tranceivers have an internal pull-up from pin A to VCC and a internal pull-down from pin B do GND? (with higher values?)

2) In this condition, what should be the voltage between A and B (5V)? (Considering a very high input impedance meter)

3) At question 2, the logic level at RO pin is '1', right?

4) Now, if I put just a termination resistor (120 Ohms) between A and B, the logic level at RO will be 'undeterminated', right? I think if the internal resistors are present, they will have a high value and the voltage between A and B will be near to 0V due to the low resistance of the termination.


I really have these doubts a long time.
Someone can help?

 

[KeepItSimpleStupid]

Woah! Some wording here: "undeterminated" is not a word. It is "undetermined" or unknown or can be anything.

It says if the input is Open Circuit, the output is high. The termination resistor creates a connection.

 

[esm.]

Here is my current schematic, attached in PDF and PNG.

I would like to design this schematic for use in RS-485 buses with a maximum of around 64 nodes.

I have some doubts about this schematic yet:

1) For R3 and R8 (fail-safe biasing), I am using 560 Ohms. Somebody know which are the most commom values used for fail-safe biasing?

2) Also for R3 and R8. I am using through hole resistors (250mW / CR25 body). Could I change them to 560 Ohms SMD 1206??? (because I am already this SMD value). That would be great!

3) Would be more suitable connect the fail-safe resistors directly to EIA485_A and EIA485_B nets, instead of connecting them to A and B nets ???

4) Maybe would be better to change the values of resistors R5 and R7 (inrush protection) ???

5) The differential voltage between A and B lines of an RS-485 bus is +- 5V, according to MAX487's datasheet. Is it recommended to place a 5V TVS diode between A and B nets? Like a SM05 TVS diode, for example? For differential protection?

Some recommendations for this schematic? Change components values?

 

[KeepItSimpleStupid]

Looking at it briefly, I might change:
1) U2 to an OPTO schmidt trigger.
2) Put Enable/C/Disable positions, so at least the jumpers don't get lost or enable positions and disable positions even though one side of a 4 pin header might not even go anywhere. It's just a place to store the unused jumper.

 

[esm.]

Hi.
About your reply:

1) Do you have a recommendation of logic opto?
2) I didn't understand

 

[KeepItSimpleStupid]

1) something like: http://search.digikey.com/us/en/products/H11L2SR2M/H11L2SR2MCT-ND/446019

2)
X X Enable
X X Disable

Place the shunt across the top two x's for enable. Place the shunt across the bottom 2 for disable. The disable pads dont connect to anything, so it allows storage of the shunt.

or
E C D

Place link between E and C to enable and between C and D to disable. D doesn't connect to anything.

 

[esm.]

Now I understand. But is not a problem if there is no place to stores the jumpers. The way I am using the pin header, I can store the jumper, just by connecting one of the jumper pins to a pin of the pin header and leaving the remaining pin floating. The jumpers will be placed just in one node (fail safe biasing just in one node PCB) during the setup of the network.

 

[KeepItSimpleStupid]

What might happen years in the future, someone might see the jumper "OFF" and decide to connect it. I don't think it would cost you much in components and/or real estate to consider 3 pins instead of just 2 labeled accordingly.

I did not mention the possibility of using DIP switches, but they are considerably more expensive.

I used a LOT of boards from the DC PDP-11 computer which either used jumpers or wire wrap pins back in the day.

Looking for that elusive jumper in a pile of junk was also a problem. Wire-wrap could not be easily changed and thus in some ways it was useful.

Just consider the option. It doesn't cost much.

 

[esm.]

Yes its a good ideia.

Do you know, if in a CAN bus, who uses ISO-11898 electrical standard, a fail-safe biasing is needed?

 

[KeepItSimpleStupid]

Not exactly, but this white paper https://www.electro-tech-online.com/custompdfs/2012/05/slla159.pdf seems to indicate that an open termination should be tolerable. Look at the end of the document. Then I'd look at the specific hardware documentation that's referenced.

 

[esm.]

About the termination in a CAN bus (ISO-11898 electrical standard) is OK, but I mean to say about the fail-safe biasing with external resistors in a single node, like is required in a RS485 bus to force the receiving circuit of the transceiver to a logic level 1 when the bus is iddle.

I think is extra work the need to instal a fail-safe biasing in a single node through jumpers. Maybe a CAN bus doesnt require it

 

[KeepItSimpleStupid]

See pdf page 4: https://www.electro-tech-online.com/custompdfs/2012/05/AN00020.pdf

 

[esm.]

Understand.
These tranceivers were designed to have an internal failsafe biasing. Good.