Probably the resistor from Gate to 0V helps to discharge FET's Gate-Source junction capacitance, and probably it helps to swing gate and drain signal efficiently, isn't it JimB?
No it isn't Willen !
It is to do with the biasing of the FET.
FETs like the MPF102 and 2N3819, for correct operation they should be biased so that the gate is negative with respect to the source.
In this respect they are just like thermionic valves where in normal operation the grid is negative with respect to the cathode.
Have a look at the circuit fragment which I have attached to this post, it is a simlified version of what I drew in post #6.
Conventional current is flowing through the FET from the +ve supply to the 0v line via the drain and the source.
As that current flows through R1 (yes there are two of them, take your pick!), a voltage is developed across the resistor as per the usual V = I.R Ohms law thing.
When we connect the gate to the 0v line, either by a high value resistor, or the low resistance of a coil, the gate is connected to the -ve end of the resistor and the source to the +ve end of the resisitor.
And so, we magically have the correct biasing for our FET, gate -ve W.R.T. source.
The term for this type of thing is "self biasing" or "source resistor biasing".
JimB