Question on parallel interface timing.

[Eclipsed]

I'm trying to send data,in parallel, to a Noritake VFD display.I've always found these parallel timing diagrams confusing.The datasheet is here:

**broken link removed**


I would appreciate if someone could maybe explain this to me.This is what I make of it(I'm only communicating one way, so I can leave the WR pin on the display grounded right?):

1. Set data bits
2. Lower CS
3. Delay ?
4. raise CS
3. poll BUSY pin, wait until its no longer active, then wait 2 uS?, goto 1

Is this correct? What are the meanings of the other minimum times? Should I swap 1 and 2?

 

[Dialtone]

From the perspective of the program to send the data to the port/device, the following general sequence applies (bi-directional port).
1. Read the status register busy bit, if state is OK then; (/CS on the display unit)
2. Set the printer port control register to send data
3. Write the data register bits D0-D7
4. Write the strobe bit (hold it for at leat 5 us) (write on the display unit)
5. Clear the strobe bit
6. Clear the data bits (optional step)

From what I gathered on the data sheet, it appears you need to delay 200-700us between data word transfers to allow the parallel input register to be shifted out serially to the display controller.
You can get more info on parallel port operation by going to
http:\www.beyondlogic.org and studying the links provided under legacy ports header
Dialtone