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Pure Logic Gates Basketball Scoreboard

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asbf - thanks for the effort, but you're not quite there yet. The monostables have to hold the astable 555 in reset to guarantee that it always starts with a complete cycle. In other words, the gating has to come before the astable, not after it.

ak

Thanks, and now I see the problem and how to solve it. That's why when I press the step 3 button, sometimes I got 4 pulses. I tried to sync the start of pulses of the astable 555 using its reset pin to start the pulsing from the 555 mono-stable trigger pins through AND gates but it didn't quite work as I planned.

So, I'd leave it for the OP to solve this synchronization problems.

Allen
 
I think the initial intent of the 555 timer is for a button debounce (555 setup as a one-shot) .... but as mentioned above if you have say four 555 timers, where one of the four is a base timer (sort of like a one shot but triggered from the other three 555 timers) ... the base time is the longest time interval. the other three 555's have an interval that is a multiple of the base interval .... i.e. one of the three would only be able to produce one pulse within the base interval, while a second one would be able to produce two pulses, and lastly the third 555 would be able to produce 3 pulses within the base interval.... the over all function of the pulses would be "gated" by the base interval and effectively have a debounce built in.
 
In your circuit, the rate at which the score advances within a single gate would vary depending on the number of increments above one point. Don't know if this is better or worse than evenly-spaced pulses, which take a varying amount of time to complete an update.

As an extra-credit puzzle, generate 1, 2, or 3 evenly-spaced pulses into the 7490 clock input using only two 555's.

ak
 
In your circuit, the rate at which the score advances within a single gate would vary depending on the number of increments above one point. Don't know if this is better or worse than evenly-spaced pulses, which take a varying amount of time to complete an update.

As an extra-credit puzzle, generate 1, 2, or 3 evenly-spaced pulses into the 7490 clock input using only two 555's.

ak
I think it can be done by connecting the 3 buttons to the RC of the monostable 555. Will try it out later..

Allen
 
Here's my first trial but didnt work very well.

I've also tried 4066, 74HC238 in place of the 3 PNP transistors, but they are worst than using the BJTs.

SCORE_B_v2.PNG
 
Hello. I've seen the responses and I am thankful for the help. As I said earlier, I'm completely a newbie in this subject and I'm just absorbing infos from all of your answers so bear with me if I dont understand some terminologies :3
 
So i did a study last night and Ive made this circuit but i cant seem to make the 74192 counter to decrement, here is my circuit plese advice
upload_2018-3-9_11-48-22.png
 
Here is a circuit for the requirements in post #1. It requires that you release the 2 and 3 buttons before the circuit is finished updating the 7490, or there might be extra pulses. This can be fixed by adding a differentiator to the U2 ans U3 inputs, similar (but not identical) to the U1 input. Let me know if you want this.

ak
Scoreboard-1-c.gif
 
The same functions can be achieved with two CD4093 quad Schmitt trigger NAND gate ICs and *no* 555's.

But if you're really loony, the entire circuit can can be done with only one CMOS hex inverter (and six diodes).

ak
 
Here is the NAND gate version. It looks more complicated than the schematic in post #33, but actually has fewer parts and fewer connections. Seven, 2-input NAND gates in two IC packages. Because the 2 and 3 inputs are true monostables (unlike a 555), you can hold down the button as long as you like and the counter will be clocked only 2 or 3 times. Same for the 1 input.

U1A and U1B (and U1C-U1D) form a true monostable. A negative edge at the input produces a negative-going pulse at the output. These are OR-ed (and inverted) in U2A. (Through DeMorgan-s Theorem, a positive-true-input NAND gate equates to a negative-true-input OR gate.) So U2A pin 3 goes high when either 2 or 3 is pressed, but for different times. This enables the U2D oscillator, which starts with a negative-going edge. The 1 input also produces a negative-going pulse, and this is OR-ed with the oscillator output and inverted in U2B to produce positive-going clock pulses for the 7490.

ak
Scoreboard-2-c.gif
 
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And finally, here is the circuit in post #35 reworked to use a single IC, a CD40106 hex Schmitt trigger inverter. The OR and oscillator-enable functions are done with diodes and a resistor.

ak
Scoreboard-3-c.gif
 
And finally, here is the circuit in post #35 reworked to use a single IC, a CD40106 hex Schmitt trigger inverter. The OR and oscillator-enable functions are done with diodes and a resistor.

ak
View attachment 111504
Using one 40106 to replace 3x LM555 was a big trade off and simplified the circuit much. I wish the OP has learned much from this thread. At least I have.:D

Allen
 
Using one 40106 to replace 3x LM555 was a big trade off and simplified the circuit much.
Not as much as you might think; all of those diodes add up. Still, it was fun to work out. Not counting the three switches:

555's - 52 pin connections -- 18 components

4093's - 52 pin connections -- 14 components

40106 - 50 pin connections -- 19 components

So from a total labor point of view, the 4093 circuit easily wins the "complexity" category. The number of pc board pins to solder is almost a wash, but the number of things to insert confirms what I suspected: the 40106 circuit is cute, but the allure of a "single-chip" circuit is deceptively inefficient.

ak
 
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