Pulse Delay

[qwertyqwq]

Hi Folks

Im working on some pulse delay circuitry but couldnt handle yet , so need some help over here !

Currentl i need a delay time,when every time pulse applied. The delay time will approximately about 1uS to 100uS. Already searched on internet aand found a scheme which was ok for me but . Im saying ok cause the circuit is reversing the pulse and it is decreasing positive width. I desided to try in real and the result was so much weird. Cause the circuit is working with 555N but not working with 555P !!Here is the scheme of the circuit. In my country i couldnt find out 555N so my plan failed.

Now i found a old post from here and desided to ask you guys is there any other strong method to implement a pulse delay without changing pulse ? Im saying strong cause the circuit will work far from me ))
Here is my pulse ranges;
Freq: 2Hz..130Hz (variable freq )
Dutycycle: %30..%80
Voltage: 5V--12V ( actually 8 V is ok for me )

 

[rjenkinsgb]

What resolution do you need - eg. does it matter if the delay time is not absolutely synchronised and there is a fractional jutter?

The simplest way I can think of is use a shift register with an adjustable frequency clock to set the delay.

https://sub.allaboutcircuits.com/images/04408.png

eg. Using a 74HC595 the delay would be 8 clock periods but with the output always changing in time with the clock.
**broken link removed**
Cascade 2, 3 or more and you can make the delay 16 or 24 clocks etc.

They will work up to at least 25 MHz with a reasonable supply voltage, so with 24 stages (three ICs) the delay coudl be as low as one microsecond and as long as you like.

At the shortest delay the jitter would be around 40nS, as 100uS delay about 4uS.

 

[AnalogKid]

It is not clear what you want. For example, do you want to delay both the leading and trailing edges? By the same amount?

Please post a sketch of the input and output pulses that you want. Depending on what you post, the circuit might be as simple as an R-C delay and two Schmitt inverters.

ak

 

[rjenkinsgb]

Depending on what you post, the circuit might be as simple as an R-C delay and two Schmitt inverters.

That's exactly what the other circuit he links to uses: https://www.electro-tech-online.com/threads/adjustable-pulse-delay-circuit-phase-adjustment.113461/

 

[qwertyqwq]

It is not clear what you want. For example, do you want to delay both the leading and trailing edges? By the same amount?

Please post a sketch of the input and output pulses that you want. Depending on what you post, the circuit might be as simple as an R-C delay and two Schmitt inverters.

ak

yeah i should give more infos ,sorry.

For example the pulse has 200uS on time and 200uS off time (400uS period). I want to make a pulse like 180uS on time. I mean i want to create something like deadtime. By the way im also looking for a pulse phase difference circuit.

That's exactly what the other circuit he links to uses: https://www.electro-tech-online.com/threads/adjustable-pulse-delay-circuit-phase-adjustment.113461/

I was doing this circuit in pratical. But couldnt get what i want to make.Let me explaine what i got from that circuit.
I simulated the circuit via Proteus 8 and its working exactly i wanted. R1 is varying delay time of rising edge, and the R2 is varying delay time of every fall edge of pulse. If you vary two of them synchronously you are making phase difference. That was perfect in simulation and this is all good for my desire.
Now in practical , i used 74HC14 for hex schimtt inverter against of cd40106. (There were no difference in simulation. ) In practical i can only vary delay time of rising edge about 200uS and more. Not less then 200uS. Max rising edge delay time is huge like 5-6mS. The problem i need 1uS to 100uS delay time. And also when i use a capacitor between Vcc and GND of ic , the output signal reversing with no reason that i couldnt explain ! And also when i decrease R1 less then a few kiloohms , i got a freq divider. The period of the input signal is , on time of the output signal (half of the freq).

I hope i could explain,what is my problem. Sorry for my english

 

[rjenkinsgb]

Now in practical , i used 74HC14 for hex schimtt inverter against of cd40106. (There were no difference in simulation. ) In practical i can only vary delay time of rising edge about 200uS and more. Not less then 200uS. Max rising edge delay time is huge like 5-6mS.

The actual delays will be proportional to the circuit R-C time constants and in the example the values give relatively long delays.
Changing the caps to eg. 330pF should give nearer the times you need.

 

[qwertyqwq]

The actual delays will be proportional to the circuit R-C time constants and in the example the values give relatively long delays.
Changing the caps to eg. 330pF should give nearer the times you need.

I got it master thanks.
But i should learn something. How did you calculate cap value ? Is that Tau equition ?

 

[rjenkinsgb]

Good to hear it is working!
The minimum time was 200 times too long, so 1/200th of the original 0.1uF ( = 500pF) as a starting point.

Then adjust that down a bit more to allow for stray capacitance and some "spare" range at the lower time end of the scale...