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Propagation delay on quad NAND gate

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renzen

Member
Hello,
On quad NAND gates, all of 4 NAND gates have same/identically propagation delay or each of them have different propagation delay?
If each of them have different propagation delay, is there a quad NAND gates where all of 4 NAND gates have same/identically propagation delay?
Thank you in advance.
 

alec_t

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is there a quad NAND gates where all of 4 NAND gates have same/identically propagation delay?
No. Since all of the gates are from the same small region of a silicon slice they will have almost identical properties, but imperfections in the silicon and the manufacturing process will inevitably result in slight differences. For most applications this is of absolutely no consequence. What critical application do you have that would require identical propagation delays?
 

Tony Stewart

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Are you designing a race condition? ;)
If you need really low delays, use current mode logic ( CML )


edit..

Also differences in load capacitance will affect rise times and apparent delay.

HC logic is around 300 Ohms
ALC logic is around 50 Ohms.
 
Last edited:

ronsimpson

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I think most NAND gates will not say what the difference in delay is.
Knowing how they are made inside, I think the difference will be very very small.
The data sheet will say what the slowest part is, typical, and fastest. (parts made years apart)

I think the difference in delay will be much slower then the rise time.
 

spec

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Hy renzen,

Where are you from? Care to put it in your profile page nect to 'Location' so that it shows in the window at the left of your posts.

The propagation delay will also vary with chip junction temperature, actual supply voltage on the pins of the chip (0V and Vcc), the impedance of the 0V and Vcc lines, the source impedance and rise time of the circuit driving the gate. The impedance of the supply lines should be defined locally by a ceramic capacitor which will have a capacitance highly dependent on temperature, and voltage. This will also affect the propagation delay. And finally, the output loading, with all its dependencies, will also affect the propagation delay.:D

spec
 

renzen

Member
alec_t
Thanks. Just a normal project and I'm just wondering :D

Tony Stewart
Something like that :D
Thanks for the info.

ronsimpson
Thanks for the info.

spec
I'm from south east asia.
Yeah, there's many factors affect propagation delay. I'm just thinking if using quad NAND gates where it has identically propagation delay, it will increase the accuracy.
Maybe I'm just too perfectionist :D
 

alec_t

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I'm just thinking if using quad NAND gates where it has identically propagation delay
As you can see from the above posts, it won't be possible. Any competent circuit designer has to take into account component tolerances when designing a circuit. It is bad practice to design something which requires zero tolerance in either the components or the operating conditions.
 

MrAl

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alec_t
Thanks. Just a normal project and I'm just wondering :D

Tony Stewart
Something like that :D
Thanks for the info.

ronsimpson
Thanks for the info.

spec
I'm from south east asia.
Yeah, there's many factors affect propagation delay. I'm just thinking if using quad NAND gates where it has identically propagation delay, it will increase the accuracy.
Maybe I'm just too perfectionist :D

Hi,

Increase accuracy of what?

Yes there will be tolerances on the delays present.

Another issue related to periodic timing is "jitter". That's the change in timing caused by various things like delays that change for example. It becomes more important at the frequency goes up.
 

Misterbenn

Active Member
as an interesting note, they use to use this type of race condition as a random number generator. Slight differences in junction temperature, voltage and any number of other things would cause cause slightly different propogation delays down two identical paths and this would be used to set 'random' bits in a register.

This isn't used in high end encryption any more as it was found that with some knowledge of the enviromental conditions the results could be predicted with some accuracy, a real life demonstration of chaos theory.
"Chaos theory concerns deterministic systems whose behavior can in principle be predicted. Chaotic systems are predictable for a while and then 'appear' to become random."
 

Tony Stewart

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Most Helpful Member
My 1st introduction to CMOS race conditions was a programmable timer circuit for portable seismic recorder that could be selected for recording inervals and durations, designed by a post grad Physics student when I was debugging the 10 units after he got the prototype working. Due to wide variances in vendor tolerances, his design failed and I had to fix it. Motorola was slow and Fairchild was fast. The metastable or race conditons caused asynchronous counter detection glitches and errors, so I had to invert the counter clock used as a sampling clock to outputs gated to a FF to force a race to win worst case.

This is the most common need to understand component delay variances
, which we call a " tolerance stack up" of all delays, set-up , hold and rise/fall time & skew tolerances for the every timing state change in a design to look for (invalid) "race conditions".
 
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