power-delay product in CMOS

[PG1995]

Hi

Could you please help me with this query? Thanks.

Regards
PG

 

[MrAl]

Hi,

Arent they talking about the highest possible switching frequency? In that case you dont have the option to lower the frequency. That would make sense because the most concern is at the highest possible frequency which gives us a means to compare technologies and quickly see the result of changing the voltage or capacitance. If we instead investigated every frequency we'd find that the most important one is the maximum operating frequency partly because all logic families dont dissipate much power at 1Hz, and the voltage and capacitance dont change that too much at that low f.

 

[PG1995]

Hi MrAl

It looks like either I'm not understanding what you said or there is a possibility that you misunderstood my question. I have tried to rephrase my confusion. Kindly give it a look and help me. Thanks.

Regards
PG

 

[MrAl]

Hello,


Yes i agree, but that's because again you are including frequency not max frequency. It's no mystery that if you lower the frequency you lower the power dissipation, and because it's no mystery we dont need to look at that. What we need to look at is what happens at the max frequency, and that is of primary concern. So when we say the lower bound it's because we are putting a lower bound on the power dissipation at the max frequency. In other words, at the max frequency we can prove that there will always be at least some power dissipation like x watts where x is always going to be greater than some constant.

Lets see if this helps...

For a certain gate we have calculated three power dissipation levels at the max frequency: 0.9 watts, 1.1 watts, 1.2 watts. We are not sure which one it is because of some of the variables in the equation we used to calculate the power dissipation. We can't say for sure what it is, but we know after we consider all variations that we have one of those three. We might be making an error because of the unknowns, so at least we want to know what the best possible power dissipation is that we could ever see, so we chose the lowest one because we know for sure that it can never go lower than that. So if we hoped to use this in a real life circuit, we might be shooting for 1 watt, so then we might have a chance at seeing this criterion met. However, if we calculated the three as: 1.1 watts, 1.2 watts, 1.3 watts, then we know for sure that we could never meet the criterion of 1 watt because the lower bound is 1.1 watts.

So in a real life situation we might be faced with finding out if there is any hope of ever getting this gate to work at the max frequency when we consider the space and air flow restraints we have available to dissipate the power. If the lower bound says "no", then we know we cant do it. If the lower bound says "yes", then there is a chance it might be doable.

It seems that any question about this would come from the 80 percent factor they threw in there. By stating "lower bound" they are implying that the 80 percent is a minimum factor, such that if that goes above 80 percent the power dissipation goes up. So by implication the word 'approximately' may not be the best choice of words.

 

[PG1995]

Thank you, MrAl.

t seems that any question about this would come from the 80 percent factor they threw in there. By stating "lower bound" they are implying that the 80 percent is a minimum factor, such that if that goes above 80 percent the power dissipation goes up. So by implication the word 'approximately' may not be the best choice of words.

I believe you have it right. It's the word "approximately 80 percent" which is causing all this confusion because it sounds like as if it can't go above 80%. Moreover, I'm sorry because I just noticed that I didn't include a related important figure with my question which could have helped you to help me.

The book says that the overall performance of a logic family is ultimately determined by how much energy is required to change the state of the logic circuit. The traditional metric for comparing various logic families is the power-delay product, which tells us the amount of energy that is required to perform a basic logic operation.

So, now I take it that when that text says "lower bound power-delay product " it is really saying that practically PDP will be be greater than this theoretical calculated value. The reason for this could be that rise and fall times could account for more than 80 percent of transition time. Please correct me if I'm wrong. Thanks.

Regards
PG

 

[MrAl]

Hello again,


Reading this again it appears that they want us to take that 80 percent as written in stone where it can be 79.9 or 80.1 for example, so 80 would be used no matter what.

What this would mean is that the only other variable is the T, which they state:
T>=5*Tp

and then go on to state:
PDP>=CV2*Tp/(5*Tp)

which implies that PDP might be greater than CV2/5. So if PDP was greater than CV2/5 that must mean that T<5*Tp which is not reflected in T>=5*Tp because that's the very opposite.

Lets say that the upper bound is PDP_U. Then what can we say about PDP? All we can say is:
PDP<=PDPu

and lets say that the lower bound is PDP_L, then what can we say now about PDP? We can say:
PDP>=PDP_L

so this means that CV2/5 must be a lower bound because they state PDP>=CV2/5.

Now if we go by the first inequality:
T>=5*Tp

and normalize this (and the other inequality) for Tp we get:
Tn>=5

and we can plug that into:
PDP>=CV2/Tn

Now lets see if it holds:
PDP>=K/Tn {Tn>=5}

PDP>=1/Tn {Tn>=5}

If we make Tn=5 we get:
PDP>=1/5

if we make Tn=6 we get:
PDP>=1/6

and it is obvious that PDP got smaller so PDP could not have been a lower bound if T is allowed to increase.

This is one of the reasons why i like to condone the use of redundancy in teaching lessons of any kind. It's because the author's intent is not always super easy to determine without referring to additional secondary text.

Perhaps they are just trying to define a lower bound without paying strict attention to how they got there. What we are not really sure of is what parameter that they want to vary in order to define this lower bound. If it is truly 'T', then the statement does not seem correct.

What is sure is that PDP=C*V^2*f*Tp and that is equivalent to PDP=C*V^2*Tp/T and T is approximately calculated as T=5*Tp.

As a matter of fact i'd rather see an upper bound equation so that i would know if the device is going to overheat. So perhaps they did make a mistake in the wording.

Other thoughts:

They might actually be trying to specify that as the speed AND frequency of the IC increases (better IC chip means faster clock rate too for comparison) the power goes up, so that PDP actually is a lower bound. So it's like a comparison of technologies rather than a comparison between operating points of a single technology.
This was my original thought anyway. If we could somehow view the whole chapter we might be able to figure this out for sure because we'd have more context to work with.

The design process itself would focus on a particular gate technology. An equation like that for PDP would be used, the total for the package would be calculated, and the comparison made to the rated total power dissipation of the package at the expected ambient temperature. If the design works it would not exceed the rated package dissipation, so it's as simple as that. But if they are not focusing on the design process but rather on a range of technologies, then we have a different view.

From Shakespeare's Hamlet we have the quote:
"brevity is the soul of wit"

but it's unfortunate that brevity is also the source of much confusion.