notwist said:
Can anyone help me understand the difference between the lock and capture ranges of a PLL system? From what I've read so far, the lock range is essentially the range of frequencies in which the VCO frequency is the same as the frequency of the input signal. Is this correct? If so, then what does the capture range specify?
Let's imagine that you have a working synthesizer that operates at about 1 MHz using a 4046 chip as the phase detector, a 12 bit programmable divider in the feedback, a reference (phase comparison) frequency of 1 KHz, and using a separate VCO. Power supply voltage is 5 volts. Let's say that the VCO was designed to have an input control voltage range of 0 to 5 volts. At 0 volts, we will say that the VCO was designed to operate at 600 KHz and at 5 Volts it was designed to operate at 1400 KHz.
Let's say that under normal conditions with the divider programmed to divide by 1000, this PLL operates at 1000 KHz with a control voltage of 2.5 volts. Now, if you change the divider to divide by 610, then the VCO frequency will be forced down to 610 Khz. Since this is within the range of control input of the VCO everything continues to work fine, and the control voltage is now at 0.0625 volts. Now, what happens if I program the dividers to 560? The phase detector will attempt to output -.25 volts but since it can only go down to 0 volts, the loop will fail to lock and the output frequency will be something other than 560Khz but unlocked so therefore unstable and wandering around. So now we see that the "lock range" of this synthesizer is the frequency range of the VCO. This is the range of frequencies in which the loop remains locked.
Ok, so what is the capture range? This is the range of starting frequencies from the VCO over which the loop is able to correctly begin to push the loop into lock. Imagine that you have just applied power to the system, the dividers happened to power up to a value of 0, and the VCO powers up at the bottom of its range, at 600 Khz and the loop is unlocked. Now, let's say that you then program the dividers to 1090. What happens then? Well, it depends on the phase detector. I specified that we are using the 4046 as a phase detector, but in fact there are two kinds of phase detector in the 4046. The so-called phase detector I is a simple exclusive-or gate. It outputs a pulse stream that is exactly 50% duty cycle when the two inputs are the same frequency and exactly 90 degrees out of phase. If you study this phase comparator carefully you will discover that as you vary the difference between the comparison and reference frequencies with this phase detector, there are many frequencies over which it will not work. This is dependent on the phase relationship of the inputs as well as the bandwidth of your low pass loop filter. With this phase detector the capture range is typically less than the lock range and is dependent on the low pass filter as well as the input frequencies.
However, if you use phase detector II, you will find that there are no frequencies at which this detector will give a false or incorrect output. You can see these details on page 11 of the CD4046 data sheet (here
https://www.electro-tech-online.com/custompdfs/2007/11/CD4046BC.pdf ). With this phase detector, the moment we program 1090 into the dividers, the loop filter output voltage will ramp upwards until the loop locks.
So, if it were me actually designing a PLL, I would use Phase detector II. With this phase detector, the capture range is the same as the lock range.