What is the correct way to place and connect decoupling caps on a 4 layer board? Top and bottom layers for routing, L2=+5V L3=GND. SMD and DIL packages. I've put the packages on the top layer, and the caps (100 nF 1206 smd) under the packages, on the bottom layer.
The DILs power pins connects directly to the inner layers. How should I route the caps for optimal result? Directly down to the power layers, or to the IC pins? It's my first 4 layer board. I'm used to place decouplings as close to the ICs as possible and connected directly to the power pins.
your caps are not great for high frequency systems, nor for fine pitch parts.
while most sample layouts you see show 0402 or smaller on the bottom side directly under the pins, I have never considered that optimal since the tiny via has a higher inductance than the nonexistent trace to a 100pF decoupling cap
It's not as critical when you are using the inner layers for a power plane and ground plane - they have a distributed capacitance effect that inherently reduces noise.
If you can get all the surface mount parts on the top it will save you money in assembly charges.
It's not as critical when you are using the inner layers for a power plane and ground plane - they have a distributed capacitance effect that inherently reduces noise.