This would be an error, but when referencing any register, you would use 00-7Fh, and the PIC would access the bank as set by bit RP0 in the STATUS register. This is because there's only 7 bits in the instruction to hold the register address, so to access more than 128 bytes/registers, they need to be banked.reg1 equ 20h
reg1 equ A0h
bcf STATUS,RP0 ; Clear the bank bit
bsf 05h,0 ; Sets bit 0 of GPIO
bsf STATUS,RP0 ; Set the bank bit
bcf 05h,0 ; Clears bit 0 of TRISIO
When you enter your interrupt service routine, you don't know what bank you might be in at the time, and you need to save the W register before making any changes to the bank bits, therefore, you need to reserve that byte in both banks. But, on the 16F629 it doesn't matter, since the general purpose registers are the same in both banks.The user register, W_TEMP, must be defined in both banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x20 in Bank 0 and it must also be defined at 0xA0 in Bank 1) "
Because, once you've saved W off (in either bank), you then move STATUS to W (in essence saving it), and then you can change the bank bit in the STATUS register, eliminating the need to reserve space in both GPR banks. Once the bank is set, you store W to STATUS_TEMP which saves the original copy of the STATUS register. Here's the sample code from the datasheet:also, there is written that "The user register, STATUS_TEMP, must be defined in Bank 0." why is this so? why only in bank 0?
MOVWF W_TEMP ;copy W to temp register,
could be in either bank
SWAPF STATUS,W ;swap status to be saved into W
BCF STATUS,RP0 ;change to bank 0 regardless of
current bank
MOVWF STATUS_TEMP ;save status to bank 0 register
:
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into
W, sets bank to original state
MOVWF STATUS ;move W into STATUS register
SWAPF W_TEMP,F ;swap W_TEMP
SWAPF W_TEMP,W ;swap W_TEMP into W
Certain commonly-used registers such as STATUS, FSR, PCL, and a few others are mirrored in both banks to make them accessible without having to switch banks.in the memory map there is written that status register is in both bank 0 and bank 1!.. so what does this mean? is status in bank1 a reflection of the status register in bank 0 or what(other examples are the FSR PCL and PCLATH, i really wonder why they are in both banks )??
The only way timer1 will continue to increment during sleep is if you use the Timer1 crystal oscillator. See page 33 of the datasheet.inally,
i need to make myself sure about two other things with regards to the sleep function:
1.in section 9.7 the datasheet says that theoscillator driver is turned off... now, timer0 is surely turned off during sleep, but with regards to timer1, if say an hs oscillator is used, does this mean that the timer1 won't continue to increment(since the HS oscillator driver is switched off) will it only continue to operate if the internal oscillator is used as a main oscillator??
The interrupt enable bit for the timer will cause the PIC to wake-up from sleep when the timer rolls over and its interrupt flag gets set (make sure to clear the interrupt flag before going to sleep, or the PIC will awaken immediately). If the global interrupt enable flag is set, the ISR will execute after the PIC wakes up and executes the instruction following the SLEEP (it's suggested to put a NOP there). If the GIE flag is clear, the PIC will wake-up but it won't execute the ISR; it will just resume execution at the instruction following the SLEEP. If the TMR1E timer interrupt flag isn't set, the timer won't wake-up or interrupt the PIC.Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding
interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed
therefore if the micro would in such a case wake up but not start the ISR ?
While sleeping
{
If timer1 overflows { set TMR1IF }
If TMR1F is set and TMR1E is set
{
Wake-up
Execute instruction following SLEEP
If GIE is set { goto ISR }
}
}
The PIC12F629 has 2 banks, with some SFRs in one and some in the other. The GPRs are the same in both banks (on the 629, but not on all PICs), so when you use the GPRs on the 629 you don't have to worry about switching banks.
Like blueroomelectronics said, use the include file constants to reference the SFRs and the bits within. Also, use the banksel directive to switch banks as needed (say, to access TRISIO and then GPIO).
This would be an error, but when referencing any register, you would use 00-7Fh, and the PIC would access the bank as set by bit RP0 in the STATUS register. This is because there's only 7 bits in the instruction to hold the register address, so to access more than 128 bytes/registers, they need to be banked.
So, for example (I'm using 05h to set an example, you should use the include constants to make the code more readable):Code:bcf STATUS,RP0 ; Clear the bank bit bsf 05h,0 ; Sets bit 0 of GPIO bsf STATUS,RP0 ; Set the bank bit bcf 05h,0 ; Clears bit 0 of TRISIO
You can see both GPIO and TRISIO are accessed at the same address (05h) but in different banks.When you enter your interrupt service routine, you don't know what bank you might be in at the time, and you need to save the W register before making any changes to the bank bits, therefore, you need to reserve that byte in both banks. But, on the 16F629 it doesn't matter, since the general purpose registers are the same in both banks.Because, once you've saved W off (in either bank), you then move STATUS to W (in essence saving it), and then you can change the bank bit in the STATUS register, eliminating the need to reserve space in both GPR banks. Once the bank is set, you store W to STATUS_TEMP which saves the original copy of the STATUS register. Here's the sample code from the datasheet:Certain commonly-used registers such as STATUS, FSR, PCL, and a few others are mirrored in both banks to make them accessible without having to switch banks.Code:MOVWF W_TEMP ;copy W to temp register, could be in either bank SWAPF STATUS,W ;swap status to be saved into W BCF STATUS,RP0 ;change to bank 0 regardless of current bank MOVWF STATUS_TEMP ;save status to bank 0 register : :(ISR) : SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into W, sets bank to original state MOVWF STATUS ;move W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W
reg1 equ 20h
movwf 20h
movwf A0h
Yes, you are correct, for the PIC12F629. But some higher-end PICs have more memory and the banks will contain different data, so something to keep in mind if you start developing things with other PICs.from the memory map there is written that A0h is actually 20h, i.e if you write to A0h you are writing in 20h actually.. therefore you cannot use A0 for something and 20h for something else right? in fact in the memory map it says
general purpose: 20h-5fh
A0h-DFh accesses 20h -5fh
they must be the same... you cannot use one location for something and its reflection for something else ...
thanks
regards
When you use movf, the Z bit in the status register will be changed. Therefore, if you're trying to save the status register, you don't want to use instructions that change bits in the status register. Swapf is a good one to use since it doesn't change the status bits.why does it use the swapf instruction instead of just moving it? someone somewhere has suggested that the status register can be changed if the status register is simply moved to w and then to its temp file.... i would really like to have an example how this is possible cause i cannot find one myself.
That's because movwf doesn't change status flags, but movf (movfw) does. Therefore, if you want to move things around without changing status bits, you need to use the two swapfs (which has the same effect as movfw without changing status bits).not mentioning that it seems contradictory(again for me) since to move w in w_temp he just used the movwf, whilst when it came to moving the w_temp back to w(after moving the status register) he used the swapf instruction twice...
Many 14bit core PICs have shared (all bank) memory at the 0x70 to 0x7F range. This is easy to demonstrate with the MPLAB simulator. It was a perfect place for W_TEMP & S_TEMP variables.
You are correct. In the case of the 12f629, all of the general purpose registers (the places you save your own data to, at 20h and higher) are shared across all banks, so you don't need to worry about switching banks for accessing your own variables. You only need to worry about switching banks for accessing certain SFRs (such as TRISA and PORTA which are in different banks).that you can simply ,if you use the shared data, set the w_temp register and status_temp register in which ever location you want and form which ever bank you want since being shared you are still writing at the same location.. and when you want to context save, you just write w_temp or status_temp, you don't have to bother about getting to bank 0 for the status register as mentioned in the datasheet. this is since we are using shared data, and thus variables in bank 0 can be accessed using the same name, through both banks using the same name in either case...
right?
thanks regards
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