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Pic SPI Interrupt ?

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We are using the spi mssp module of a 18F4520.

From when the data is moved to the SSPBUF and the next instruction to test for data transfer to complete, the SPI hardware module is in control of the data etc.
While it is in control can the normal interrupt system work without any delay or is it held up while the spi module completes its task ?

Initial tests seem to suggest the interrupts are delayed although I would have thought one of points of the hardware module was to overcome such problems ?

	movwf   SSPBUF 			; put in SSPBUF
done   btfss   SSPSTAT,BF 	        ; Data transfer complete?
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