Given this is a low power device, the only significant power that gets generated is
driving heavy load and / or oscillation.
Page 14 layout considerations followed ? I found when working with BW of this
magnitude I had to qualify the ceramics for actual performance. Using a 50
ohm jig and scope evaluated ESR, found wide variations between manufacturers.
I also notice datasheet recommendations of .1uF and Tant did not include .01 uF
ceramic. Their ESR curves broaden the effective bypass range.
You can use an SDR cheapo radio receiver, or a shortwave VHF receiver, or a Nano VNA
to look for issues if you have limited scope BW/probes.
Additionally, every fast amp has at least two poles, and any additional phase shift
adds due to stray C and Fdbk R a killer of phase margin. Stray C is not your friend.
And R parasitics can contribute.
Cap technology ESR freq performance key (even in bulk parts) -
Pic of your SMD layout.....?
The outputs look pretty good and they stay within at max ±1.5mv noise levels.
150C at package surface, and a 95C/W thermal R says to me the die is hotter than the surface of the sun.
When looking at output is your scope BW restrained to 10 - 20 Mhz, and/or you are using a 1X versus a 10X
probe ? You might not see the oscillation.
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device on a two-layer board with 2500 mm2 of 2 oz. copper at +25°C 8-lead SOIC package: θJA = 95.0°C/W. MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the AD8017 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated device is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure.
Regards, Dana.