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Op-Amp Attenuator vs Resistive Network

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Pre_Shan

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Hello All,

I have a board that produces a 0-8V analog signal. The signal is actually 0-40V, but there's an op-amp attenuator on board which reduces it to 0-8V. There is no way I can tap the original signal, and I cannot change anything on the board.

Given the above constraints, I'm designing a new board that has to process this 0-8V signal and digitize it. Most cheap ADCs are 0-5V input compatible. There are a couple of +-10V ADCs from Analog Devices, but they don't meet my other requirements of internal reference, serial communication and low pin-count.

So I guess I have to attenuate this signal further, coming to my question - Is it ok if I simply use two resistors in series as a potential divider to step this down? Or do I have to use an op-amp attenuator? If yes, is it ok to have two consecutive op-amp stages?

I'm no analog expert!

Thanks,
Pre_Shan.
 
A resistive divider will be fine. Just make sure the resistance of the divider is low enough to drive the ADC properly. A 5.1K and 8.2K resistive divider should work OK for this.
 
You'll have to satisfy the source impedance requirement of the specific ADC. e.g. for ATMEGA48 internal ADC it says any source impedance less than 10k. It differs for different ADCs.

To calculate the equivalent source impedance of the resistive divider made up of R1 and R2, use 1/(1/R1 + 1/R2) or R1.R2/(R1+R2).
 
A resistive divider will be fine. Just make sure the resistance of the divider is low enough to drive the ADC properly. A 5.1K and 8.2K resistive divider should work OK for this.
That doesn't compute. To go from 8v to 5v, the resistor ratio needs to be 3:5, not 5:8.
 
You might have to use an op-amp buffered resistive divider- it depends on how much current your signal source can output is and how high the input impedance of the ADC is. With an unbuffered divider, it's a balance between the two. You either use lower resistance and sacrifice signal integrity for sampling accuracy or use higher input resistance to preserve signal integrity while sacrificing sampling accuracy. Other than that...what everone else said.

But why would you need two op-amp stages to buffer a resistive divider? Using two buffers one after another is kind of pointless, and you don't need to buffer the input to the resistive divider since you can just use really big resistors to get high input impedance. Personally, I'd almost always buffer a resistive divider with an op-amp, but I'm pretty conservative.
 
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That doesn't compute. To go from 8v to 5v, the resistor ratio needs to be 3:5, not 5:8.
Using 24 values, I calculate 4.93V out with 8V input to a 5.1K/8.2K resistive divider which should keep the voltage within the range of a 0-5V ADC. The OP never specified how precise a divider that was required: He may want even more headroom, to compensate for resistor tolerances, or in case the voltage rises above 8V.
 
Using 24 values, I calculate 4.93V out with 8V input to a 5.1K/8.2K resistive divider which should keep the voltage within the range of a 0-5V ADC. The OP never specified how precise a divider that was required: He may want even more headroom, to compensate for resistor tolerances, or in case the voltage rises above 8V.
It is pretty close. I guess I had a brain fart. There are exact 3:5 ratio resistors, though, like 12k:20k, and 18k:30k.
 
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