Noise in non-isolated switching booster

[Maklaka]

I recently read an article in EDN by Henry J Zhang that could help me fix my 9V->12V switching booster circuit for a project. You see, I get loud, irritating audible noise from the booster circuit that delivers about 100mA.

I'm using the LT1111-12 for my DC-DC booster.
https://cds.linear.com/docs/Datasheet/1111fd.pdf

I have assembled diagrams from my project and the article into one PNG attached to this post. The full article can be found here:
https://cds.linear.com/docs/Application%20Note/an136f.pdf

I have the "old" layout implemented on the most recent rev of my board and it hums like nobody's business. I placed an HF reject (0.1uF) cap into the circuit and it definitely changed the sound but didn't by any means reduce the volume. If I understood the article correctly, I should shorten the switching loop as much as possible while beefing up the trace sizes. Therefore, I picked an SMD diode with comparable specs, stretched the traces from 50->100mils, squished the HF reject cap and diode together, and put a shielded inductor on there for good measure. In the professional opinions of the community, who thinks I'll have more luck with the revised layout as shown below?

He seems to contradict himself on why the short, fat traces are desirable. On one hand, long/skinny traces increase parasitic inductance, but on the other hand: "To minimize coupling capacitance between the switching node and other noise sensitive traces, you would minimize the SW copper" Read pages 1-4.

View attachment 67857

 

[ronsimpson]

What is all the data on the two inductors you have used?
It could be you are saturating the inductor.

 

[Maklaka]

Old/unshielded I-SAT = 2.3A
https://www.digikey.com/product-detail/en/TSL1112RA-470K2R1-PF/445-3770-1-ND/1913634?cur=USD

New/shielded I-SAT = 3A
https://www.digikey.com/product-detail/en/744770147/732-1231-1-ND/1639292

Worst case Ipeak through that inductor should be about 1.25A according to my calculations.

 

[ronsimpson]

Where is the capacitor on 9V to ground? There should be a cap form pins-1,2 to ground pin 5.

The larger and shorter traces look better. There is current in pins 2,3,4,5.

When the paper talks about smaller traces it is talking about traces like the one going to pin-8. It has only 1uA in it. Pins 1,6,7,8 have almost no current.

I would put a cap on 9V above U3 and fill the area between the pins with ground. Move the pin-8 trace to the right of U-3.

 

[Maklaka]

I do have a cap from 9V to ground but I suppose it is a bit too far away from the 12V dc-dc. I can place a 0.1uF-10uF decoupling cap near pins 1,2 (9V net) and sink a via to ground... no need for a direct trace to pin 5.

I could squeeze a sliver of the ground plane between the IC's pins but my work requires me to have fairly large space between power nets; this could complicate things.

Good call, I'll move the sense trace from pin 8 off to the right to get it away from the high di/dt traces.

Given that my 33uF Cout cap is already ceramic, is it really necessary that I use a 0.1uF ceramic for HF rejection? These designs assume that an electrolytic with high ESR is on the output so it is recommended to have a ceramic as well. Therefore, with price/size not being an issue, does it make sense to have a 33uF ceramic in parallel with a 0.1uF ceramic?

Hopefully these changes make the difference. Thanks for the tips.

 

[ronsimpson]

Try the 33uF ceramic cap from pins 1,2 to 5. Solder the cap on 1,2 and use solder wick as a wire to pin 5.

 

[Maklaka]

Okay, 33uF placed across 1/2 and 5. She still squeals.

 

[alec_t]

Does touching the inductor affect the noise?

 

[Maklaka]

Touching the inductor does not affect the noise, no.

 

[Maklaka]

Okay so here's the whole power supply section of the board. The "new layout" board has yet to be fab'd. You can see that I took another piece of advice from the article where he recommends that the shared power rail for different switchers should be split traces instead of tapping off of one trace. U1 and U2 are 3.3V and 5V switching reg "drop-ins" (with different pin outs than the linear's...seriously...) whereas U9 and U8 are the alternative linear regs.

C1, C2, & C3 have been promoted from 0805 to 1206 in the event that I need more capacitance. C19 near U3 was added for a closer decoupling to my 9V->12V.

And you can see C7 (0.1uf to 10uF) has been added to 12V out. Let me reiterate a question form before:
"
Given that my 33uF Cout (C4) cap is already ceramic, is it really necessary that I use a 0.1uF ceramic (C7) for HF rejection? These designs assume that an electrolytic with high ESR is on the output so it is recommended to have a ceramic as well. Therefore, with price/size not being an issue, does it make sense to have a 33uF ceramic in parallel with a 0.1uF ceramic?
"

Traces have been generally beef'd up and the sense lead on U3 was placed off to the right - further away from the di/dt business.

Can I get any other recommendations?

View attachment 67891

 

[alec_t]

Your layout mods may well help circuit performance, but are they likely to affect the squeal? The audio noise source has to be something electro-mechanical, and the only suspect seems to be the inductor (coil inter-winding forces, core electro-striction).

 

[Maklaka]

Well you're certainly correct that it's the inductor - but not only the inductor. From the article:

"A common problem with switching power supplies is "unstable" switching waveforms. Sometimes, waveform jitter is so pronounced that the magnetic components generate audible noise. If the problem is related to the PCB layout, identifying the cause can be difficult. That is why proper PCB layout at the early stage of a switching-power-supply design is critical."

later in the article:

"Figure 3a shows the parasitic PCB inductors in hte high-di/dt current paths. Because of the parasitic inductance, the pulsating-current paths not only radiate magnetic fiels but also generate high-voltage ringing and spikes across the PCB traces and MOSFETS. To minimize PCB inductance, lay out the pulsating-current loop (hot loop) so that it has a minimum circumference and comprises traces that are short and wide."

 

[alec_t]

Sometimes, waveform jitter is so pronounced that the magnetic components generate audible noise.

That explains how although the switching is at an inaudible frequency (~100kHz?) there can be audible artifacts. Interesting.

 

[Maklaka]

Yes. I think that moving the sense trace from underneath the LT1111 to far off the right side might make all the difference:

"To reduce the noise coupling from the power stage
to the control circuitry, it is necessary to keep the noisy
switching traces far from the sensitive small signal traces.
If possible, route the noisy traces and sensitive traces on
different layers, with an internal ground layer for noise
shielding."

Unfortunately, I opted to just place a ground plane on the bottom layer to avoid the cost of an internal plane. Maybe just moving the trace is enough.

 

[Maklaka]

I can go real crazy and make sure the sense line isn't coupled to ground or ANYTHING by giving it a nice round about on the bottom layer. As long as a little extra resistance isn't a problem...maybe this is the way to go?

View attachment 67903

 

[alec_t]

Wouldn't a lengthy sense line be more prone to noise pick-up?

 

[Maklaka]

By my reasoning, not if the alternative is a shorter trace placed CLOSER to the source of EMI.

 

[alec_t]

Hmm. I guess you won't know without actually making a pcb.

 

[Maklaka]

*duplicate*

 

[Maklaka]

Given that my 33uF Cout (C4) cap is already ceramic, is it really necessary that I use a 0.1uF ceramic (C7) for HF rejection? These designs assume that an electrolytic with high ESR is on the output so it is recommended to have a ceramic as well. Therefore, with price/size not being an issue, does it make sense to have a 33uF ceramic in parallel with a 0.1uF ceramic?

Can anybody answer this for me?