New Spice model for CD4046B phase-locked loop IC.

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Hey alec!

I tried importing your model into MultiSim and keep receiving an error message like this one:

Error: Element 'A1:CD4046B': Unable to identify XSPICE code model for simulation in netlist element 'A1:CD4046B'
Error: Element 'A1:CD4046B': Due to errors, the component 'A1' will be omitted from the simulation
Error: Element 'A2:CD4046B': Unable to identify XSPICE code model for simulation in netlist element 'A2:CD4046B'
Error: Element 'A2:CD4046B': Due to errors, the component 'A2' will be omitted from the simulation
Error: Element 'A6:CD4046B': Unable to identify XSPICE code model for simulation in netlist element 'A6:CD4046B'

This continues for a page full of lines. I am new to importing a spice model so some assistance would be appreciated!

Thank You!

Sincerely,

Michael Jenkins
 
Sorry, can't help there. I don't have Multisim and have never used it.
 
The project is as complete as I can get it without field testing. I don't have a 4046 to play with. Post #17 has my latest model.
 
Nice. Thanks for the offer. How about the test circuit in my first post? That was intended to enable most of the IC functions to be checked.
It's 2 years since I first drew up the model, so I'll need to give myself a refresher course on its operation .
 
Take your time, should not be an issue.

Please confirm circuit. I believe the original asc file was a little different (had PC1 connected and PC2 disconnected... might have had other changes)



 
Circuit confirmed. Just move/link the input/output connections and components as appropriate for whichever phase-comparator/input/output is of interest.
 
Hi alec_t

Here is my breadboard and the results. I have not really looked at the datasheet yet so unclear whether this is correct. Only change was 9.09k as I could not find 8k2. Please note that my scope defaulted to x10 probe so divide.

I will try again tomorrow. Thinking back there was an issue with the sig gen

i started setting up as VCO and ran out of time


 
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OK I had to boost my sig gen, it doesnt trigger until it hits at least 300 mV. It looks like this close up and it goes up in amplitude with the sine wave when backed out. I zoomed in and found about 9V in 160 nS approx 55V/uS. I took out the cap for that, which gives a nice square wave.

 
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The output wave triggers when the AC sine wave is at least 300 mVpp (it's capacitor coupled) to signal in

The output is from PCII out.
Vdd = 9V
 
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Are your scope shots taken before or after the VCO has locked on to the input signal?
This is what I get when PC2 is used with the low-pass filter R3C3 to control the VCO. The yellow trace is pin 13 (PC2) output. Phase lock occurs at about the 30mS point.
 
Wolframore said:
I've lowered the freq to 2.7 kHz and this is what I get.
Click to expand...
Is that the pin 13 voltage?
Your scope seems to have locked on to the sub-harmonic.
Did you also increase R1 (to ~390k)? With R1 at 100k and Vin @ 2.7kHz the oscillator frequency is outside the lock range.
Decreasing the Vin frequency increases the time for lock to occur. You may want to decrease the R3C3 time constant if you want lock to occur in < 1 sec.
A good place to see when lock occurs is pin 9. You should see a decaying sine-wave there. No decay = no lock.
 
Yes that was on Pin13,

Ah I see, It was with R1 @ 100k. And this is a challenge to scope. I will put pin 9 on a second channel. Perhaps I should just use a 1M pot on R1 that way I can just adjust the lock
 
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