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New Spice model for CD4046B phase-locked loop IC.

Discussion in 'Circuit Simulation & PCB Design' started by alec_t, Sep 24, 2016.

  1. alec_t

    alec_t Well-Known Member Most Helpful Member

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    The current Yahoo LTspice User Group's model does not model the VCO section fully, so I home-brewed one which better reflects the functionality as set out in the Texas Instrument Application Report SCHA002A and the datasheet. I've uploaded the model and ancillary files to the User Group, but attach them here if anyone wants to play. Any bug reports gratefully received.

    Edit: See post #9 and revised model posted there.
     

    Attached Files:

    Last edited: Mar 6, 2018
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  2. Mikebits

    Mikebits Well-Known Member

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    Very nice of you to share your work :)
     
  3. alec_t

    alec_t Well-Known Member Most Helpful Member

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    Thanks. Hope someone finds it useful.
     
  4. dave miyares

    Dave New Member

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  5. Teleno

    Teleno New Member

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    I do find it useful although I believe there's a bug: for some reason the PC2out is pulsing between Vdd/2 and Vss, not between Vdd and Vss as it should. I looked at the netlist but couldn't figure it out, perhaps you can take a look at it.

    Thank you!
     
  6. alec_t

    alec_t Well-Known Member Most Helpful Member

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    Thanks for the bug report.
    Here's what I get when I run the Test file I included in post #1.
    PC2out.PNG
    Seems ok to me. Before lock is achieved the pulsing is 0V to 5V as expected. Whether the phase difference is positive or negative will determine whether the pulses are predominantly above or below the prevailing mean point. The PC2 output is a three-state one, so becomes biased at the capacitor voltage of the low-pass filter attached to PC2. This tends towards Vdd/2 as lock is approached.

    [Edited]
     
    Last edited: Mar 2, 2018
  7. Teleno

    Teleno New Member

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    You're right, I misinterpreted the waveforms. Thanks for the clarification. Great model!
     
  8. dave miyares

    Dave New Member

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  9. Teleno

    Teleno New Member

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    Yesterday I wired up a CD4046B on a breadboard to verify a simulation made with your model. The circuit didn't work, but it did when I inverted VCOout (after CompIn).
    The same simulation using a 74HTC4046 model (file attached) produced the correct polarity of VCOout.
    So I concluded that your model may need to invert the output VCOout and invert the input CompIn in order to match the component.

    P.S. to use the 74HTC4046 model properly, you must define a parameter VCC, which this model uses for digital levels.
     

    Attached Files:

  10. alec_t

    alec_t Well-Known Member Most Helpful Member

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    Thanks for that. Datasheets don't tell all. Nice to have it field tested, as I wasn't able to when I created the model. I'll look into it.
     
  11. alec_t

    alec_t Well-Known Member Most Helpful Member

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    Ok. Have modified the model as you suggested. Works ok in sim, but i'd appreciate it if you could compare its performance with the real IC and let me know the outcome.
    Revised model attached.
     

    Attached Files:

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