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Need Help with opamp Integrator Design

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Does this mean that
The time-constant of the settling time is determined by the component values and the real circuit response should be quite similar to simulation.
Does this mean that the settling time of the integrator is too large for a 10MHz input signal?
 
Zc=1/(2pi f C)

1/10K + 1/100k = 1/9.1k for matching input impedance to ensure zero Vio from Iin bias.
 
Zc=1/(2pi f C)

1/10K + 1/100k = 1/9.1k for matching input impedance to ensure zero Vio from Iin bias.

I understood this part but how would I use Z(f) for calculating gain? I thought the output of an integrator is 1/R1C multiplied by the integral of the input voltage.
 
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With these component values the output of the integrator still deviates significantly from the ideal values. I have attached the output of the integrator for a PWL file with inputs 0.1V,0.2V....1V at 0.1us intervals. The output deviates from expected theoretical results. Is this normal? Can this be corrected for?
 

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To test an Integrator , you sweep it from DC to 1MHz
At 500KHz when you start with a negative pulse, a "true Integrator has no Rf feedback resistor and positive voltage ramp begins that returns to zero and does not go negative. If you introduce a 3mV (5 max) input voltage offset due to mismatched source R on (+) it will integrate forever with a true integrator. In your case the gain is 10.

The overall gain , Av= --Zf/Zin = -(1/sC)//Rf) / Rin for feedback R =Rf
where as a true integrator is simply -1/sCRin as Rf=∞

upload_2015-3-18_6-20-52.png


Here I started the input 500KHz square with not shown with neg. polarity so ramp out is + then I closed switch which reduced DC gain from >1e+6 to 1e+1 or 10. so the output DC went to match the ref Voltage on (+) input, or gnd.

A true Integrator might use a dump switch when using low frequency signals since the RfC breakpoint defines the lower f limitation of the integrator.
 
Could you please tell me what happens if I give an AC+DC voltage input to an integrator?
The AC portion is integrated and the DC portion will be amplified by the DC gain of the amp circuit, which, in the example, would be an inverting gain of 10.
 
The AC portion is integrated and the DC portion will be amplified by the DC gain of the amp circuit, which, in the example, would be an inverting gain of 10.

Can I design a circuit that could integrate the DC and AC component of the signal simultaneously?
 
Also if I give a DC signal to the integrator it produces a Ramp. Doesn't that mean its integrating the DC signal and not just amplifying it?
 
Also if I give a DC signal to the integrator it produces a Ramp. Doesn't that mean its integrating the DC signal and not just amplifying it?
Yes, it integrates the DC signal with an RC exponential curve until it reaches an output voltage as determined by the DC gain (Rf/Rin) or the op amp saturates, whichever comes first.

If you want a pure integrator for DC then you need to remove the feedback resistor leaving only the feedback capacitor, but that will eventually saturate due to circuit offsets unless the integrator is periodically reset, or has feedback to prevent that.
 
Yes, it integrates the DC signal with an RC exponential curve until it reaches an output voltage as determined by the DC gain (Rf/Rin) or the op amp saturates, whichever comes first.

If you want a pure integrator for DC then you need to remove the feedback resistor leaving only the feedback capacitor, but that will eventually saturate due to circuit offsets unless the integrator is periodically reset, or has feedback to prevent that.

So I can still use the above circuit to integrate AC+DC signal but I have to ensure that the integrator doesn't saturate. Can I put a FET switch across the opamp to reset it periodically?
 
So I can still use the above circuit to integrate AC+DC signal but I have to ensure that the integrator doesn't saturate. Can I put a FET switch across the opamp to reset it periodically?
Yes, a FET or CMOS switch is often used across the cap to periodically discharge it (called Integrate and Dump).
But note that the capacitance feedthrough from the switch will introduce some offset error after the reset, depending upon the switch and integrate capacitor value.
 
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