Here is my hack at it. I am assuming that S2 comes from a contact closure. The circuit has more-or-less symmetrical delays on both rising and falling edges of S2. Note I(L1) relative to V(s2) in the plots.
The delay is ≈R1*C1, so you could use a 1meg pot for R1 or change C1 as needed. If you want asymmetric delays (separately adjustable) , then you can replace R1 with two pots and steering diodes. M1 is old-school NMOS like a IRF510 which has a Vth of ~4V (not logic-level like more modern ones). The relay is almost any 12Vdc relay, even the 85Ω automotive sugar-cube type would work.
View attachment 105094
I have attached the LTSpice file so you can play with it...