'NE555 P' Reset pin problem

I have set up the 555 astable MW to generate AF signals as shown in the attachment.
The intended function is that When StD control signal goes logic HIGH AF signals are permitted
to appear at + output. When StD is logic LOW, AF signals get suppressed at output.

But in practical when StD is LOW, AF signals not suppressed at output.
So I manually connect 4th pin to GROUND, then the signals get suppressed at + out.

So I am going for an OR gate as a replacement of Q4 & R9. One pin is always LOW, other one
connected to StD control.

Does have any idea about the problem ? I think Q4 open condition doesn't bring GROUND
condition at active low RESET pin.

Attachment- NE555

For starters, you need a pull-down resistor to pull the Reset pin low when your transistor is off.

I'm not sure what you're trying to do.

Just adding an emitter follower to the reset pin won't do anything, even if you did use a pull-down.

If you want to reset when A OR B goes low, connect the reset pin to 0V via a pull down and connect both inputs via diodes to form a diode OR gate.

If you want to reset when A OR B goes high, connect the reset pin to +V via a pull-up an either use two transistors to pull it down or a single transistor and a diode OR gate.