This question is because of reduced number of interrupts on a micro. I have 3 signals that are low active and only one interrupt. I need to be able to sense every lowering edge of the signals. If I use a nand gate, I will have a problem sensing a second lowering edge because the nand gate output is already set by the first lowering edge. I could use a regular port (GPIO), put I wanna avoid sweeping on the code.
Is there a hardware that could help me interface the signals?
I assume you mean you have three inputs that trigger a common single interrupt when any of the three ports goes low.
I also assume you have checked the particular processor to see if it has a configuration for the interrupts.
How do you plan on inputting the three separate interrupts assuming you externally generate them? If you want to avoid scanning code you will need three other interrupt generating ports on the micro, in which case you probably don't need an external hardware solution.
Upon reading port, immediately clear interrupt so it is ready to catch another. Some micros clear interrupt automatically on port read. You will be vunerable only for the few micro clock cycles between the two instructions. Better then this requires three independent interrupt ports.
In the old days they would use a Priority Interrupt Controller A priority interrupt controller like the 8259. I think you could also do this in SW on your cpu chip of choice, but this will depend on your needed poll rate.
Check this link.
The usual interrupt is a way for a peripheral device to signal the mcu, saying, yo I need some service here. Now anding all IRQ's to one line would create a situation for the mcu, which device is requesting service? I suppose any interrupt generated could initiate a service to all 3 peripheral devices, but this would be a misuse of efficiency and speed. Again, if you can sacrifice the service of all 3 devices per IRQ then I suppose it is no big deal.