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Motors and MOSFETs

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You are correct in that it would take an extremely high voltage to go from cut-off directly to saturation. But you never go directly there; you have to go through the ohmic region first. While this transition is happening, you are starting to get some Id flowing, which will reduce the Vds voltage drop. This is then going to require less of an increase in Vgs to reduce Rds even further, and also why the Vgs to Rds graphs are curves.

I'm not saying you go directly there, I am aware of how graphs generally work :D

I'm just saying, since Rds is "small" then the transistor sees "about" 30V and thus you need 10 or so volts to get to be fully on
 
10V seems to be the designed "on" gate voltage for most mosfets. There are logic level ones that are designed for a better 2.5-5v gate voltage range also. They cannot handle the higher drain voltages though (which I now understand why. :D) Hard to find them above 100V or so, where 400V "standard" mosfets are not uncommon at all.
 
No, you want ohmic region for switching. The many responses on this thread should make that clear.

For your motor, using 10V on the gate should be sufficient to drive your fet into the desired ohmic region. Once current starts flowing, Drain voltage will drop quickly to a much lower voltage. You will no longer have 30V across the motor, as there will be a very small drop across the fet channel's resistance, but the motor voltage should be very close to 30V, and the fet's collector voltage will be less than 1V.

Okay, where in the ohmic region then?

the pictures below explain why not to use the saturation mode (the channel is pinched off in saturation mode)
IV CURVE: File:IvsV mosfet.png - Wikipedia, the free encyclopedia
OHMIC REGION: File:Mosfet linear.svg - Wikipedia, the free encyclopedia
SATURATION/PINCH-OFF: File:Mosfet saturation.svg - Wikipedia, the free encyclopedia

So where in the ohmic region do you want to force the transistor? The point where the channel is the "widest" at all points, so, far enough away from saturation that the drain end of the channel does not start to get narrow. But, not so close to the off state that the channel is not as wide as it could be.

I assume that since the channel is "wide" (thick? deep?) at the desired operating point, Rds is low so VDS changes very little for large changes in drain current Id. Thus 10V makes the channel wide enough that no change in drain current will cause a significant reduction in VDS to appreciably change your position on the I-V curves. (perhaps a better wording is "shape/position OF THE I-V curve" (no s) )
 
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The ohmic region ( also know as the linear region ) is VGS-VT > VDS. If you apply 10V to the gate, and the VDS falls below 10V-VT, reasonable for many loads, then you are in the ohmic region. For a 30V, 1A motor, that should not be a problem.
 
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right, so VDS is defined by the current through the channel times the channel resistance. Assuming an RDSon of 1Ω just for easy numbers, and Vth=3V which is nominal...

1A * 1Ω = 1V
10V - 3V = 7V
7V > 1V !

which puts you comfortably in the ohmic region

if your load changes and current were to jump to 5A

5A * 1Ω = 5V
10V - 3V = 7V
7V > 5V !

still ohmic! this assumes that for the larger current your temperature stays the same. also Rds(on) of 1Ω is a (very) large estimate, its just for round numbers.


think I've got it now, it was the pinch-off thing that made it click. all my experience with mosfets is as amplifiers! had to get my head past that.

Thanks all!
 
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This is an application where a MOSFET is being used as a switch. To make a MOSFET look like a switch, you want it "hard on" or "hard off", neither of those states is found in the "ohmic region". Per your Fairchild PDF, on page 9 figure 6, you want to be operating on the left side of the graph... what they call the "active" region. This is where your I²R losses during "on time" will be the lowest. The faster you transition thru the "ohmic region" to the "active region", the lower your "switching losses" will be (switching losses can be sometimes higher than I²R losses). This means you want lots of current available for the gate... look at "total gate charge", not gate capacitance when calculating the gate resistor.
 
That damn graph is confusing. Took me hours to finally understand what is being shown. I think it's because it looks too much like a Vgs-Rds (or Vgs-Id) graph, which always made me think in those terms.

Saturation for MOSFETS is not gate saturation, but channel saturation. You just can't get any more current through it. Also, pinch-off starts at the saturation boundry; they are the same, which is why you do NOT want to be in saturation. That was the other big "epiphany" that helped in understanding.

I think for all practical purposes we can just throw all this away at this point. Unless you need the linear characteristics, just use the Vgs-Rds graphs from the datasheet to determine your drive voltage. Either way, the higher the drive voltage the lower your Rds_on will be, although with diminishing returns above ~10V (or 4-5V for logic level.)
 
**broken link removed**

Where it says... "For the power MOSFET to operate as an analogue switching device, it needs to be switched between its "Cut-off Region" where VGS = 0 and its "Saturation Region" where VGS(on) = +ve."

Per Fairchild AN9010… “ Saturation region: A constant current region. It is at the right side of the Vgs-Vgs(th)=Vds boundary line. Here, the drain current differs by the gate-to-source voltage and not the drain-to-source voltage. Hence, the drain current is called saturated.”

You want to be at a point where increasing Vgs further doesn't increase drain current anymore. In the "ohmic region" a change in Vgs causes a change in drain current. You don't want this condition in a switch. MikeMI’s simulation clearly shows that as the drain voltage falls (or as the gate voltage is increasing) the drain current starts to rise. That “power-bump” in the lower trace is “switching loss”. What’s missing is the gate voltage trace… so you can’t see its rise time. A slow rise time translates to high switching losses… you want lots of current to get you beyond the ohmic region quickly to minimize switching losses. Ideally an operating point just beyond the "ohmic/active boundary"

MOSFET's operating in the ohmic region is the basis of how "active loads" work... i.e. variable resistor, or "heaters" if you like.
 
Who wrote that turtorial? It doens't make any sense, since RDS isn't valid for saturation region. The power bump in Mike's simulation shows high power dissapated in that region. It's not a trun on transient. His sim steps through cut-off, saturation ( high power dissapation ) and finally into the ohmic region ( low power dissapation )

I suggest your look over the fairchild PDF linked earlier in this thread. Pay particular attention to which region in which RDS is defined. Others have done this, and they understand who ohmic is the correct region. It's a tough read, but entirelly worth the effort.
 
Mike's simulation shows the transistor going from cutoff THROUGH the ohmic region and THEN to the saturation mode. Ohmic region is the "sloped" part of the Id-Vds graph, where Saturation is the "flat" part on the right side.

You cannot get to saturation mode without traveling through the ohmic region, unless you have an infinite current source to charge the gate in an infinite amount of time!

The power bump shown in the simulation is the power dissipated in the transistor as it is traveling THROUGH the ohmic region, on its way to saturation. Once saturated the voltage at the drain is minimized and the current through the transistor is maximized. Since the VDS is minimal, you have low power dissipation in this region.
 
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It says between cut-off and saturation in the tutorial. But the point you want to be at for switching is the ohmic/saturation boundry itself.

If you're to the left of the boundry, you'll raise Rds and cause more disipation. If you head to right of the boundry, you'll start effecting pinch-off and your current will be reduced. The pinch-off effect is what the Fairchild paper is talking about when saying "...the drain current differs by the gate-to-source voltage..."

Raising Vgs pushes the boundry to the right, which expands the Rds range, as well as reducing the pinch-off effect of being in saturation. But the boundry is the sweet spot.

Again, for all practical purposes, this is moot. Just drive the gate with 10V+ and it's going to be the least amount of power dissipated, which is the goal of this excersize. :)

EDIT: LTSpice of all three regions. Mikes sim doesn't show the pinch-off effect in the saturation region.
 

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You're making this too complicated. To minimize dissipation, you want to move to the left (lower Vds), on the Id/Vds curve, assuming constant Id.

Every (without exception) Vgs curve is above and to the left of the one below it. Do the math. It works.

Conventional MOSFETs are specified for worst case Rdson at Vgs of 10V. This is all you need to know. Use the "typical" charts at your own peril. Interpolate at further peril.

"Logic Level" MOSFETs Vgs which follow these same rules; they are just at lower voltages.

Understanding the physics is a bonus. But when doing a real design, do not confuse yourself with the physics. Those formulae that give six-digit precision have to be factored with 35% or more of process, temperature, and other factors when the device is in a real circuit.

Move left. Higher Vgs.
 
You don't know if your Mosfet is "typical" like the graphs in the datasheet or if it is minimum spec. So why not use the recommended gate-source voltage of 10V?
Then super sensivtive Mosfets will turn on well, typical ones will turn on well and minimum devices will turn on well.
 
why not use the recommended gate-source voltage of 10V?
I bet you always use the recommended brand of soap powder in your washing machine and drive your car at recommended 29.99 mph in a 30 mph zone whatever the situation! :)

Taken to extreme, if you always register all the worst case interpretations of all the worst case parameters simultaneously, you end up with a design that's too expensive to build, an aeroplane that's too heavy to take off, and a manufactured product that's not competitive in the marketplace!! If you don't cut costs, your competitors will!

If a MOSFET chosen outperforms its requirements by a huge amount in some parameters in the application, means that some of its driving requirements can be less 'standard'. = lower gate drive voltage

In practice, a "100 A, 5mohm @ 10Vgs FET" is found to have the same price and quality level as a "10 A fet", which is chosen for doing a "1A job", this allows it to only need 5 V or perhaps logic-level gate drive.
 
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Taken to extreme, if you always register all the worst case interpretations of all the worst case parameters simultaneously, you end up with a design that's too expensive to build, an aeroplane that's too heavy to take off, and a manufactured product that's not competitive in the marketplace!! If you don't cut costs, your competitors will!
This needs to be done intelligently. Using a 100A MOSFET so you can get away with 5V Vgs at 1A Id (your example) is rarely economical.

Remind me not to fly in your airplane with flight controls that usually work!
 
Even passenger aircraft are operated with compromises on 'safety' for reasons of economics. For example in my experience, every Captain of a passenger jet has a different opinions of such things how turbulent it has to be to order return to seat + seatbelts, and when you can and can't use cellphones in his plane. It's his call he's the one who's responsible.

Using a 100A MOSFET so you can get away with 5V Vgs at 1A Id (your example) is rarely economical.

Yeah the tone of my example was a bit extreme, but you've got to agree it's often more economical in the long run to use higher ID fets.

Here's an example from my experience. The circuit my Engineer 'designs' (more like lifted from somewhere) spec'd an IR IRFS4620PBF in it, which our buyer found OK this exact one £1.29 for 100 pcs, assuring me it has all the right suffixes in the part number, so it will work 'as designed'. His nicely-computer drawn circuit which impresses everyone he shows it to, I notice has now acquired extra power rails in it for his religious "10 V gate drive" and a fancy power sequencing system that 'protects' the FET should there be a failure in the any one of these extra supply rails he added, the design is beginning to look 'top heavy' this last week he's been working on it, so I'll take over and give him break (otherwise this project will run over budget). But that was after a 'guided realisation experience' with your truly as the Guide, trying my best not to damage his morale. (I'd rather he was slightly wrong and happy, than always right)

So I checked the datasheet myself and this IRFS4620PBF was Id(max)15A, and Rds(on)="78 milliohm". The VDS isn't much of an issue, because it's only 7.2 V we're dealing with.


OK, that's an old FET design, it happens to us all.

So I find these instead:

Fairchild FDB8441 100 pcs. £1.28 (a penny cheaper).
Id Cont:28A (double)
On State Resistance:0.0019ohm (can ditch the heatsink now)
Vgs th Typ:2.8V

I keep looking:

Fairchild FDB8447L 100 pcs. £0.35

Id Cont:50A
On State Resistance:0.0085ohm
Vgs th Typ:1.9V (can ditch the top heavy paraphenalia too)


And see this too:

STM STP140NF75 100+ £1.14

Id Cont:150A
On State Resistance:0.0075ohm
Vgs th Typ:4V


But to me it's not about the design, but the Designer.
 
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