Motorola HC08

[Lada]

Has anybody worked with Motorola HC08 family ? I think it's very good CPUs. Much better than PICs, ATMELs ....

 

[kinjalgp]

What special is there in HC08 CPUs that makes it superiour than ATMEL and PICs? Most of the CPUs I saw has OTPROM instead of reprogrammable FLASH ROM. I hardly found any development board for these CPUs on the net. The one which motorola sells is a non-real time debugger which is useless when developing time-critical applications. Also I have found only one schematic for programming these devices. Rest are universal programmers which support this family.

The only plus points of these uCs are low power consumption and low cost due to use of OTPROM.

 

[subzero349]

another thing I like about the HC08 is the instruction set... I think it is much easier to understand and use then PIC... I hate switching banks... plus, in my experience you can do the same thing with the hc08 and it takes up less memory than a PIC would...

 

[Chippie]

horses for courses and personal preference......... :wink:

 

[Lada]

I like very much these things

- simple ICSP in-built programing
- perfect in-circuit debugging
- debugging without programing into FLASH !!!.
- in-built USER MONITOR MODE in ROM.
- CodeWarrior - C/C++ language is to 4 kB free
- large instruction set, CISC with Von Neumann architecture
- all HC08 family has same CPU08

but bad things, Motorola has very small advertisment for these componencts, so nobody know about them (aspecialy in CR)

 

[TheAnimus]

Thank you Lada in 3 words u have warned me off these products for life.
"Von Neumann architecture"
**** on a stick is also a good technical term.

also CISC, thats another bad word.

okay for the un-enlightend, Von Neumann designed this cheapscape arcitecture in the 70s, which has no real cost benefit today, only makes things slower. The idea was you only have one memory bus for the program and data memory. This means that you can't pre-fetch the next instruction, because you might need to use some "data" memory (think File registers in PIC speach) but of course u couldn't do that if the next instruction was been fetched.

In short Von Neumann architecture = bad, for uC applications avoid like the plauge

 

[soupwizard]

okay for the un-enlightend, Von Neumann designed this cheapscape arcitecture in the 70s, which has no real cost benefit today, only makes things slower. ... In short Von Neumann architecture = bad, for uC applications avoid like the plauge

Actually, that's wrong. Nearly every computer designed since the 60's uses a variant of the Von Neumann architecture. See:

https://www.wikipedia.org/wiki/Von_Neumann_architecture

Maybe you're thinking of some low-cost architecture for small processors that has those restrictions you mentioned, I don't know what that would be called.

As for CISC vs RISC, I don't think it matters in processors this slow. There's no deep pipelining going on, and the clock isn't very fast, so the chip designers can't take advantage of scheduling the simpler instructions of a RISC processor.

[Edit: Now that I think about it, maybe I'm not correct on the CISC vs RISC thing. As far as I know, RISC came into being because as clock rates get higher, it become much more difficult to scale a CISC instruction set. So by reducing the instruction set to simple actions, a chip designer can pre-execute and re-order the simpler instructions to run faster.]