The substrates silicon wafers for CMOS are usually P type doped silicon for improved insulation, but when the input or outputs of CMOS exceed the supply threshold of 1 silicon diode their is an SCR Thysristor switch effect with a PNPN vertical layer junction which effectively is a shoot-thru failure between Vcc and Vdd. Since CMOS has been made upto today, they use Schottky diodes on all inputs to each rail to shunt this and inhibit this failure mode often caused by ESD or any source of voltage > 0.5 V outside the supply rail. JUst like in voltatile memory logic and Thrystors alike this memory effect is cleared when supply is removed and so the failure mode stops and normal operation resumes.... unless the metallic layers and semiconductive doping layers are fabracated to give lower ESR, then the net ESR is low enough to cause the chip to exceed 150'C and the epoxy to start to smell, or even get hotter and start to crack.
We always used mixed vendors in HCxxx CMOS during the 70's& 80's but knew if we wanted fastest performance to use certain vendors like Fairchild becuase they had lower ESR , slightly more current drive but also slightly more self-destructive when an SCR latchup incident took place. One such time was when we were field testing a SCADA , ISDN broadband WAN with AMR, teleshopping and graphical weather data and a high speed serial port to the TV for the class of computers in those days that we had such events. Static on the TV and discharge to the remote serial keyboard to the cards in the basement which experienced SCR latchup. The ones like Motorola CMOS which had 300 Ohms per port at 12V would not fail but get warm, and others like Fairchild with less than 150 Ohms per port ESR would get too hot and self-destruct. We were able to fix the ESD problem with better ground wire to the basement to the TV channel changer serial port and keyboard for teleshopping.
But it wasn't until years later that I understood why some were more likely to be non-destructive than others. Vcc^2/ESR= Pd and 1Watt into a chip rated for 250mW was going to rise 4x as much. This all has to do with the design of the chip and its doping concetration levels and the effective RdsOn of each switch and the inherent defective SCR latchup effect from over voltage. Not only can you get latchup on an input stage , but also an output stage ( but harder ) YOu can also toggle the state of a Flip Flop by back drive an ESD pulse into Q from ESD, which is why we must use an extra inverter to buffer Flip Flops driving long wires to prevent this defect in design, inherent in all CMOS logic for Flip Flops.
Even those the planar junctions are depletion mode FETS, the vertical layers when biased outside the supply range form the SCR latchup effect with bipolar characteristics.
Now today for bipolar transistors if we want exceptionally low saturation resistance in a driver , we use FETs but if the switching capacitance is too high and we need high voltage, we turn to Transistors made by Xetex (or now Diodes Inc) super-saturated devices with Rce values in milliohms so with 1 Amp it is now possible for Vce to be <20mV. Although different than RdsOn for a FET, the patents are similar in describing the doping and channel topology which makes their devices better but also much more expensive but low Vce/Ice and high Vce ratings with very low capacitance
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