Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Micro processor/controller core discussion.

Status
Not open for further replies.
'People' aren't calling it CISC, only one person is making such a silly suggestion, the PIC is a RISC chip - and has a smaller instruction set than the AVR.

I suppose it was I who misspoke... what i meant is that it is of the same caliber of an 8 bit CISC. and ancient sluggish chip that might has well be a CISC for the hoops you need to jump through to do something as simple as sticking a constant in the code I think it was.

unless the 18s are better than the old ones having a 16 bit instruction word instead of a 12, then the statement stands. Harvard architecture can only go so far toward salvaging the corners that were cut as a necessity of the times.
 
Last edited:
I suppose it was I who misspoke... what i meant is that it is of the same caliber of an 8 bit CISC. and ancient sluggish chip that might has well be a CISC for the hoops you need to jump through to do something as simple as sticking a constant in the code I think it was.

unless the 18s are better than the old ones having a 16 bit instruction word instead of a 12, then the statement stands. Harvard architecture can only go so far toward salvaging the corners that were cut as a necessity of the times.

The newer ones (PIC18) do have 16 bit instructions and extended mode addressing for use with the C compiler.
 
I suppose it was I who misspoke... what i meant is that it is of the same caliber of an 8 bit CISC. and ancient sluggish chip that might has well be a CISC for the hoops you need to jump through to do something as simple as sticking a constant in the code I think it was.

Still seems that you have it confused.

A RISC processor has a less complex (smaller) instruction set. RISC may take 2 or more instructions to do what CISC can do with one.

A RISC processor will make you jump through more hoops than a CISC.

The idea was that RISC cores could be clocked faster and use as few as 1 clock per instruction when CISC machines were taking several. Given that we now can cheaply buy all the speed needed this is mostly a moot point in the 8 and 16 bit units.

Given that we mostly program in higher level language, having a chip with just the right combination of peripherals is more important then what is under the proverbial processor hood.
 
Still seems that you have it confused.

A RISC processor has a less complex (smaller) instruction set. RISC may take 2 or more instructions to do what CISC can do with one.

A RISC processor will make you jump through more hoops than a CISC.

The idea was that RISC cores could be clocked faster and use as few as 1 clock per instruction when CISC machines were taking several. Given that we now can cheaply buy all the speed needed this is mostly a moot point in the 8 and 16 bit units.

Given that we mostly program in higher level language, having a chip with just the right combination of peripherals is more important then what is under the proverbial processor hood.

that i am well aware of. I would say that while there is the literal meaning of CISC and RISC, I would call most modern ones CISCy RISCs. Th original idea was more that just one instruction per cycle, it was also low transistor count.

A CISCy RISC goes nuts with addressing modes instead of with specific instructions. Is a move that can move a whole table in a single instruction the same as a single character move instruction? The ARM core does pretty much that, a single move instruction and a single branch test instruction to move a block of data. So did, for that matter the DEC PDP11, the Motorola 68000, the TI 9900, and the Atmel AVRs to varying degrees.

A full CISC would have you set up specialized registers that waste transistors for just this instruction before you execute a block move.

A DEC PDP11 has you set up general purpose registers (a source, a destination and a count) and execute a move with repeat and auto increment or decrement on the source and destination addressing. An ARM requires you to copy to internal registers, but still has the pre or post increment or decrement. The TI 9900 was a weird bird in that instead of internal registers it kept a register set address register that got stacked while the real "registers" were in RAM.

A full RISC in it's original concept would have very few address modes as well as it's namesake of very few instructions. Early RISC machines did so little in a single instruction that it often took 20 or 30 instructions to do fairly basic operations. Back then that was not considered a big deal since common CISC machines like the Intel 8080 had to do a lot too for all their complexity.

It is a common comment in professional discussions that the line between CISC and RISC has become blurred. Along these lines if you add an instruction in microcode to a RISC machine does it become a CISC? Or should ARM 32 bit code no longer be called RISC since they could take so much out of it to make ARM THUMB? (ARM7 machines had both ARM and ARM THUMB instruction sets, THUMB being 16 bit codes that went through a translator, and the CORTEX cores took out the 32 bit support entirely)
 
I am in agreement with everything you said. Once one moves into modern processors the literal meanings are at best blurred. I tried to indicate that.

I had a HeathKit H11 (LSI-11/03) started with paper tape upgraded to the 8 inch floppy system. I loved that machine.

Also had a PDPll/05 with a hard drive with one fixed and one removable platter. When I got it the HD controller did not work. Narrowed it down to a counter that did not generate a signal when the requested data had been transferred. Minutes after I replace the bad chip a guy showed up to look at the HD. He was a local tech that worked on the computers used at grocery stores. He screwed it up so that it generated over velocity errors. A bit of a crime in that I had just got it working. Ended up selling the HD to the people he worked for. The 11/05 is at a friends.

EDIT: I enjoyed you last post. I have not kept up with the 32 bit cores. Was tied to a desk working on small Motorola's when they arrived.

How do you feel about MIPS ?
 
Last edited:
I am in agreement with everything you said. Once one moves into modern processors the literal meanings are at best blurred. I tried to indicate that.

I had a HeathKit H11 (LSI-11/03) started with paper tape upgraded to the 8 inch floppy system. I loved that machine.

Also had a PDPll/05 with a hard drive with one fixed and one removable platter. When I got it the HD controller did not work. Narrowed it down to a counter that did not generate a signal when the requested data had been transferred. Minutes after I replace the bad chip a guy showed up to look at the HD. He was a local tech that worked on the computers used at grocery stores. He screwed it up so that it generated over velocity errors. A bit of a crime in that I had just got it working. Ended up selling the HD to the people he worked for. The 11/05 is at a friends.

EDIT: I enjoyed you last post. I have not kept up with the 32 bit cores. Was tied to a desk working on small Motorola's when they arrived.

How do you feel about MIPS ?

i had a museum piece in high school ... a 16K core PDP11 with a 12" 1M platter :)

Not familiar with the MIPS, so I couldn't say.

First "machine" I ever had was the Heathkit micros course trainer.
 
Status
Not open for further replies.

Latest threads

New Articles From Microcontroller Tips

Back
Top