Matching NFETs?

[Mosaic]

Hi:
I have a hi pulse current using a bank of 4 IRFP3206 NFEts. Every so often (months) one can blow shorted.
In order to even the loading, I am looking at matching them, I have both a curve tracer and a simpler (quicker) tester.
The digital tester gives Gate capacitance (eg. 9.42nF) and Vt (eg 3.47V) in a few seconds.
What parameters should I consider matching for a switching application (700Hz) . is the tester parameters enough?

 

[alec_t]

Actual Rds(on) at the Vgs you intend using might be a useful thing to know (regardless of switching rate).

 

[simonbramble]

I don't think it is the imbalance of the FETs that is causing them to blow. If you drive the FET well past its VGS threshold, the temperature coefficient of the RDSON is positive. Temperature goes up, RDSON goes up, thus restricting the current in that FET, so it self balances. Only if the FET is in its linear mode (VGS just about turning the device on) will RDSON change negatively.

What is probably happening is that you have upstream inductance through the input cable or filter chokes. If you suddenly turn off the FET this inductance creates a back emf that puts a high voltage spike on the FET. Exactly the same as a boost converter. You switch on the FET, build up energy in the inductance, then when you suddenly collapse the current to zero V = Ldi/dt kicks in. A fast change in current with time generates a high voltage. This will blow your FETs up and it is random as to which one blows. A capacitor (10uF ceramic) immediately before the FETs or a transorb in the same place (with good board layout) will stop the problem

 

[ronsimpson]

Post your circuit/ give more information.

 

[Mosaic]

I did some research on the matter and it's probably one of three things.
1) varying Vth causing one or the other FETs to switch first, possibly solved by preselecting FETs tested for Vth.
2) Avalanche due to Back EMF, which is happening, as I understand FETs can vary by about 20% in their true avalanche voltage, they are just specified to a minimum. Testing a bank of 4, 1.5KE36CA TVS units as flywheels...but they're running over 100°C when the back emf gets going.
3) Transients (from the switching) hitting the gate due to parasitic capacitance. Reduced gate pulldown from 10K to 2.7K and moved resistor 2" closer, onto the quad gate star feed.

 

[tomizett]

This is interesting. Like a lot of people, I'd believed for a long time that FET's couldn't suffer from thermal runaway effects because they "had a negative temperature coefficient". A little while ago, however, someone here explained that thermal runaway could indeed occur with modern FETs with a very low Rds(on), as even if this increased with temperature it was still never great enough to overtake the decreasing Vgs(threshold). That's at slightly odds with what Simon is saying above, though, which is that this runaway phenominon can only occur when the FET is driven close to Vgs(threshold), as when they are driven "hard", variations in Vgs(threshold) are not significant.
I suppose the take-home message from this is that we need to read the datasheet very carefully with reference to how a device will behave across temperature under any particular drive conditions.

With regard to Mosaic's specific problem, even in the absence of thermal runaway as such, is it possible that a FET with a lower Vgs(threshold) is simply turning on sooner and off later, and therefore just dissapating more power - eventually pushing it over it's alowable die temperature?
It seems to me that in order for this to happen you'd have to be driving all the transistors very near their maximum temperatures - and I presume you're not doing that? Also, if this was happening, you should be able to measure a temperature difference between the transistors. I presume they are all running at a similar temperature?

It seems to me that differing load-sharing due to variations in Vgs(threshold) are going to be more significant with slower turn-on and turn-off times. At 700Hz you've probably not worried too much about fast high-current driving, so perhaps a faster drive would help mitigate these device variations?

If we're interested in determining whether this is (a) a thermal effect due to poor load sharing or (b) something else like back-EMF of ringing, then it seems to me that we'd be more likely to see (a) when running hot and/or heavily loaded - in contrast, if it fails shortly after turn-on, then (b) seems more likely. Probably stating the obvious here, but does that make sense?

I know (I'm sure we all know) that Mosaic is pretty competent at power switching circuits, so I presume that you're confidant there is no parasitic oscilation or ringing? Good high-current gate drive, low-inductance paths, separate gate stoppers for each FET, maybe ferrite beads, appropriate snubber circuits etc?

As a last thought, if you don't mind the continued down time, it might be interesting to characterise but not pre-select the FETs - just mark them up before installing them. Then you'll be able to see, when they fail, if there is any common factor in the paramiters of the failed devices.

Cheers!

 

[Mosaic]

The problem isn't thermal runaway, as the MOSFET that failed happened to be the one wearing the thermistor that trips off the 700Hz PWM signal (8% DC) for the switching once 90°C is attained (body temp). Normal op temps are in the 70C to 80C region. Clean square Gate waveforms driven by an MCP1407 driver backed by adjacent staggered value lo ESR caps up to 100uF.
No ground loops as the gate signal is optoisolated from the uC. The MCP1407 runs cool. 5 Ω metal film Gate resistors plus ferrite beads on the output of the MCP1407.

The MOSFETS sit on a 3/8" x 6" x 6" alum. plate heat spreader, with a 120mm, 80+ CFM cooling fan blowing crossways across both sides of the plate with the device enclosure acting as a box wind tunnel to accelerate the turbulent airflow over the FETs. It makes a fair amount of dB wind noise.
Star/hub for the Drains and ground plane with copper braid augmentation to the LO ESR cap bank (8K uF @ 9mΩ) feeding the sources.

The power delivery is enough to warm the 8x 14AWG hyperflex, audio grade, cables (2'ea) to about 50°C. Each set of 4 cables are paralleled delivering 7mΩ resistance and about 1.0 uH inductance. Pulse currents can exceed 800A as measured by a custom built Ion Physics Current monitor transformer, 40V/A into a 50Ω input on a 400 Mhz DSO.

Temperatures measured by a FLIR E8 Thermal Cam.

Spec sheet for the MOSFET
https://www.infineon.com/dgdl/irfp3206pbf.pdf?fileId=5546d462533600a401535628d64a1ff0

FET driver:
https://www.farnell.com/datasheets/2243649.pdf?_ga=1.121554753.870694276.1485566007

Power design-avalanche guidelines
https://www.infineon.com/dgdl/an-1005.pdf?fileId=5546d462533600a401535590ab660f3a

Pulse waveform


Load Battery & cable temperatures (IR thermal)

 

[tomizett]

Thanks for the info Mosaic - as expected, it all sounds very well designed. Let's see what others can suggest (I'm out of ideas!)...

 

[alec_t]

Is the blown FET always in the same location on the board, or is the location random? Same would suggest a layout cause whereas random would suggest the FETs are mismatched in some way.

 

[MrAl]

Hi,

Some considerations for paralleling mosfets are as follows:
1. Short leads between devices helps keep inductances down.
2. Symmetrical layouts keeps interconnections the same.
3. Twisted pair wiring helps maintain signal integrity.
4. Separate gate resistors reduce oscillations caused by inductance in the source circuits.
5. Snubbers of some kind, for any mosfet application that involves inductance.

There's a possibility that using a good, fast external reverse diode would work better than depending on the internal diodes. The forward voltage characteristic must be lower than that of the internal diodes.

I assume that there are already gate resistors as that is like a minimum requirement as well as adequate drivers. Each mosfet gets it's own resistor.

 

[Mosaic]

Failures appear random.
I can't achieve twisted pair outputs as resistance loss is a big consideration at 800A. I use parallel cabling to mitigate both resistance and inductance.
To date I allowed the avalanche of the transistors to limit the back emf, but I've been advised that the actual avalanche voltage varies significantly on date code. So it could be avalanche on the lowest breakdown transistor clamping the voltage and causing unbalanced avalanche and eventual early failure.
I just applied 4 x 1.5KE36CA bidirectional Tranzorbs to flywheel, max Vc = 50V. At full bore they run up to over 100 C, but that was with long leads and no specific airflow cooling design. The heating of the tranzorbs imply around 1 W dissipation on each.
I am remaking the PCB with the flywheels installed staggered for cooling and soldered to copper braid thickened traces for low resistance (electrical & thermal).

Curiously, placing a self healing X2 capacitor (.22uF) across a tranzorb caused it to jump in temperature by 50%, lower capacitances result in lower temp rise. Post back emf ringing drops in frequency significantly and elongates to over 15uS vs 10uS with no capacitor.

 

[schmitt trigger]

It would be very, very interesting if you took Vds scope waveforms, with/without any of the proposed "fixes".

Parting thoughts......Your switching frequency appears to be not very high. Have you considered IGBTs?

 

[Mosaic]

Here are the yellow Vds (rev polarity) wave forms with & w/o the 1.5KE36 CA snubbing.


and w/o snub


Blue is the 40V/A current monitor, Yellow is the Vds driving pulses into the battery load.
As far as I can tell the transorbs are only diverting some of the avalanche, not all of it.

 

[MrAl]

Failures appear random.
I can't achieve twisted pair outputs as resistance loss is a big consideration at 800A. I use parallel cabling to mitigate both resistance and inductance.
To date I allowed the avalanche of the transistors to limit the back emf, but I've been advised that the actual avalanche voltage varies significantly on date code. So it could be avalanche on the lowest breakdown transistor clamping the voltage and causing unbalanced avalanche and eventual early failure.
I just applied 4 x 1.5KE36CA bidirectional Tranzorbs to flywheel, max Vc = 50V. At full bore they run up to over 100 C, but that was with long leads and no specific airflow cooling design. The heating of the tranzorbs imply around 1 W dissipation on each.
I am remaking the PCB with the flywheels installed staggered for cooling and soldered to copper braid thickened traces for low resistance (electrical & thermal).

Curiously, placing a self healing X2 capacitor (.22uF) across a tranzorb caused it to jump in temperature by 50%, lower capacitances result in lower temp rise. Post back emf ringing drops in frequency significantly and elongates to over 15uS vs 10uS with no capacitor.

Hi,

Twisted pairs applies to the input wiring not the output wiring.

If the cap causes more heating then that could mean that it is storing energy during part of the switching cycle from energy delivered, and then any damper has to eat up that energy. Without storing any energy there would be less to get rid of. Similar to how a rectifier and smoothing cap works. The smoothing cap absorbs energy and that contributes to the total energy output. Without the cap, less energy output.

What kind of gate resistors are you using, and their values?

 

[Mosaic]

4.7Ω 2W metal film gate resistors. The FET bank is on a PCB with the FET driver, so no loose wiring.
See yellow Vgs waveform, *with* long ground lead on scope.....which picks up some noise during the ringing.


Edit:
Here is a different wave form...which is a test with a 1uF Polyester Cap & 1Ω, 1 Watt metal film RC snubber across Drain/source. The yellow trace is the voltage across the 1Ω which = Amps flowing.
The Blue trace is the actual Vds waveform which shows no ringing now. The resistor gets up to 100°C in a few secs and I suspect it will burn out if left to steady state.

 

[Mosaic]

Some more tests. revealed that a capacitor across the FET drain source CAN reduce Vds to under the avalanche voltage but a suitable size (eg. 100uF,0.050Ω ESR) overheats rapidly.
This document staes that a low Gate source resistance implies the gate oxide layer is punctured.
https://www.diva-portal.org/smash/get/diva2:18589/FULLTEXT01.pdf

A good IRFP3206 shows > 10MΩ and the blown unit shows about 84Ω gate to source, tested in both directions.
If the gate junction is blown => a fast transient crossed the Cgd parasitic (250pF) and delivered the damage or accumulated smaller transients eventually destroyed the gate over time.

 

[tomizett]

I've been advised that the actual avalanche voltage varies significantly on date code. So it could be avalanche on the lowest breakdown transistor clamping the voltage and causing unbalanced avalanche and eventual early failure.

That definitely sounds like the most likely mismatch-related mode of failure to me - very interesting. It feels like you're on the right track with investigating snubbers and keeping the FETs out of avalanche. I'm sure you've thought of this, but you could also look at an asymmetrical snubber with all/part of the resistance bypassed with a diode - this might help reduce the dissipated power.

Thanks for the link to the paper, too.

 

[shortbus=]

Just a hobbyist so this may sound and probably is a dumb question. But why use four To-247 package mosfets instead of a single "isotop" style that is made to handle the load? This is what I mean by 'isotop', it's a standard package for power mosfets.

 

[Mosaic]

I have no idea what an ISOTOP FET is. Got a link on digikey etc?
BTW paralleling MOSFETS reduces Rdson and does load sharing.

Some updates.
The BackEmf can charge a 1KuF cap (I measured the capacitance) to 36V in 40mS. Or it delivers .65J in 40mS = 16.25W
@ 700Hz that translates into 28 pulses. So 1 pulse = 23.2 mJ of kick back energy.

The capacitor tops out at 38V. Given the avalanche is happening @ 65V => the pulse diode resistance is just a bit less than the ESR of the capacitor which is around 30mΩ; based on the voltage divider formed by the two as they are in series.

However, the backemf pulse current induced voltage across the 30mΩ Capacitor ESR is up to 25V. Which is 833Amps!
The rated max avalanche current is 100A per IRFP3206 spec sheet. So this may be the problem. Even with balanced load sharing across the 4 FETs in the array, the max avalanche current per device may be being exceeded.


Having snubbed the avalanche I did some thermal tests. With an RMS of 2A, about 280A pulse over 20 to 22uS. With the snubber in place the transistors had a 3°C temp increase after 10 min.

Without the snubber and a 5uS avalanche, there is a 15°C temp increase! So the flywheel snubber certainly siphons off the heating and improves the transistor SOA.

The snubber is a bit more complex than a flywheel diode. It is a flywheel in series with a 30mΩ 50V 105 C electrolytic cap which is discharged thru a 10W G4 lamp (16Ω). The purpose is to allow for accidental reverse connection of a 12V battery load. The lamp limits the rev. current and the cap allows high flywheel current (>800A)

 

[shortbus=]

I have no idea what an ISOTOP FET is.

Can't choose one for you. You'll have to do that for yourself. Just type "isotop mosfet" into either Google or one of the electronics sellers search engines. Isotop's are real power mosfets, used in motor drives, welders and other industrial devises. The TO-247 package mosfets that are called 'power' mosfets are used in low power stuff, amplifiers and small DC things. Nothing at all comparable to a real power mosfet, other than how they work. Instead of a small lead they use a screw for the connections.

Just an example, not a suggestion. **broken link removed**