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Thanks guys for your responses. The FM band preamp example is great and proved to me that I was setting up LTSpice correctly for simulation all along. The simulation results I got for my amp from from LTSpice were so bad I didn't want to believe it and thought I was doing something wrong because I'm so new to LTSpice. For example, the output is less than the input. I was very surprised to see this because I used the procedure from the good book 'RF Circuit Design' by Chris Bowick to design the amp. The design procedure being the use of S-parameters and a Smith chart to design the impedance matching networks between the transistor and the source and load. I don't know how to design any other way. Which leads me to this question.
I do have the spice model for the the transistor I'm using(2N5179 for 162.4 MHz) but does LTSpice know what the S-parameters are from the transistor spice model?
I am working on an article explaining impedance matching using LTspice and it is based on Chris's book. It will be published on the ADI website soon.
While I cannot help you simulate the transistor itself, I can help with the impedance matching.
Looking at the s11 plot on the Smith chart on page 113, it is 40-j40 at your frequency which would imply it is capacitive.
[EDIT: I'm not sure if I have interpreted the s11 plots correctly. The rest of this post is accurate though]
So... set yourself up with a load that has a series 40 Ohm resistor and a series 24.5pF capacitor (which gives -j40 Ohms at 162.4MHz). This is the input impedance of the transistor. Do the same for the output impedance, from the s22 plot. You should then be able to calculate the impedance matching components (probably a T network) and simulate it.
Attached is a file I am playing with. Measure the voltage on the left side of C1 and the current going into C1, then divide one by the other to get the input impedance.
Right click over the left hand axis and change the plot from Bode to Cartesian. This will plot the real and imaginary components. Select the plot window (not the schematic window) and do Plot Settings -> Save Plot Settings. This will save your plot settings (duh!) so you dont have to mess with changing the axes every time you rerun the simulation. I would attach my plot file, but this site won't let me
(these instructions should be correct - I am working on a prerelease version of LTspice)
My simulation was designed to match a 50Ohm source to the input of a FET that had an input impedance of 2.1 - j4 at 100MHz. Bring up the cursors, move them to 100MHz and you can see the impedance looking into the matching network is 50 Ohms with very little imaginary component.
Thank you simonbramble for your response. I have no trouble with the Impedance matching part and since my last post I've learned quite a bit on the LTSpice simulator. I changed the spice model I was using for the 2N5179 to another I found online(Standard.bjt - LTwiki-Wiki for LTspice) and that solved the negative gain problem. I also learned how to simulate the transistor's S-parameters using LTspice. The simulated S-parameters differ slightly from the values I got from Chris Bowick's book showing the original Motorola S-parameters. Anyway, I used the simulated S-parameters and the matching methods in Bowick's book to design the matching networks. The calculated gain should be 17.3dB. When I do a transient analysis I get 17.6dB, close enough. However, when I do an AC sweep analysis, the gain simulates out to be 15.8dB.
I can't for the likes of me figure out why. Does anyone out there know?