LTSpice error

Venkat Raghav

New Member

• Mar 29, 2017

• #1

while simulating circuit in LTS, it shows error log as, "Voltage source X and voltage source X1 are paralleled making an over-defined circuit matrix".
how to fix this????
guide me plss,,,

 

crutschow

Well-Known Member

Most Helpful Member

• Mar 30, 2017

• #2

Venkat Raghav said:

how to fix this????

Click to expand...

Don't put two sources in parallel.

 

ericgibbs

Well-Known Member

Most Helpful Member

• Mar 30, 2017

• #3

hi VR,
You could add some internal series resistance to the Voltage sources, I would try to avoid putting Vsources in parallel.
E

 

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Venkat Raghav

New Member

• Mar 30, 2017

• #4

Thank u, Crutschow & Ericgibbs
it works!!!!!!!!!
thanks a lot!