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LTSpice error

Discussion in 'Circuit Simulation & PCB Design' started by Venkat Raghav, Mar 29, 2017.

  1. Venkat Raghav

    Venkat Raghav New Member

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    while simulating circuit in LTS, it shows error log as, "Voltage source X and voltage source X1 are paralleled making an over-defined circuit matrix".
    how to fix this????
    guide me plss,,,
     
  2. crutschow

    crutschow Well-Known Member Most Helpful Member

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    Don't put two sources in parallel.
     
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  3. ericgibbs

    ericgibbs Well-Known Member Most Helpful Member

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    hi VR,
    You could add some internal series resistance to the Voltage sources, I would try to avoid putting Vsources in parallel.
    E
     

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  4. dave

    Dave New Member

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  5. Venkat Raghav

    Venkat Raghav New Member

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    Thank u, Crutschow & Ericgibbs:):):)
    it works!!!!!!!!!
    thanks a lot!
     

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