[LTSpice] A timer puzzle for those with time on their hands!

So I have a buck which uses a bootstrap capacitor to switch the high FET. Sometimes I'm forcing reverse flow as a discharge feature and it could be for a while, which unfortunately means I need to blip the signal to the buck to recharge the bootstrap capacitor.

Consider the attached ltspice file. All is well for 60ms, but then there's a period of lengthy high signal. The challenge is to blip the signal twice at around the 100ms and 140ms, just briefly.



So something like..



The drain is a fast PWM signal so whatever reads it must be of high impedance.

It's almost like it needs to be a monostable and an astable but I can't put my finger on it. Be interesting to see what people can come up with!

Why the specific times 100mS and 140mS? Couldn't you just pull the bootstrap cap low at regular intervals, say every 10mS, regardless of whether your discharge feature is operating or not?

Or, could just add something like a MAX660, with an external cap and rectifier if appropriate, to provide a continuous trickle charge via a resistor to the bootstrap cap circuit?

What is the buck regulator device or circuit & what input / output voltages?

I've decided less is more and gone with alec_t's suggestion. It's not a big deal if it gets blipped when bucking.

Excellent suggestion with the MAX660, not seen that chip before and it would probably work. A fallback should I need it.