LTSpice - 74HC00 NANDs not latching like build in Digital SR

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ACharnley

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Has this been seen before? The Digital SR is working great. I then replaced it with real components, 74-00 Nands (not open drain) and it failed, so I've got the two side by side.

[outb] (incorrect) should track [outa]. It's correct up until [s1] switches (to 2.7v) at 57ms, at which point it's pulled low but doesn't latch.

 
ACharnley said:
I then replaced it with real components, 74-00 Nands (not open drain) and it failed,
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The minimum recommended supply voltage for a 7400 (as distinct from a 74HC00) is 4.75V. You seem to be giving it only 3.3V.
As with all LTS-related threads, please post your asc file.
 
I tried the sim and it works as expected for me.
Have you set Vcc=3.3 for the Nand gates?
Have you taken into account that A5 is +ve edge high-level triggered and the Nand latch is -ve edge low-level triggered?
 
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I didn't know that about the Nand being -ve, so I wonder if the slew is too great from the comparator (although the falling edge is much sharper)? It's all I can come up with.
 

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I think I have it,

There's a closed loop, the NAND toggles an output which is part of the comparator input, it causes the comparator voltage to sag slightly but enough to ensure the NAND doesn't latch. It then oscillates. Unsure how to resolve it other than a monostable before the NAND. The voltage change is enough that I can't overcome it using hysteresis on the comparator (have tried).
 

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A better screenshot.

I can't post the asc this time , too much stuff my competitors would like to see.
So the output is changing the input too fast before it latches (I think).
 
As for the sim, the LTS digital 'A' devices don't always behave as you'd expect or like their real-world counterparts. For example, if the S and R inputs of the LTS SRflop are both high, the Q output goes low, whereas for a CD4013 latch the Q and _Q outputs both go high according to the TI datasheet.

Post #4 edited.
 
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I'm sorted!, changed from NAND or NOR gates which matches LTSpice's SR gate. Something to do with the leading/trailing edge trigger, or a mystery!
 
Nearly sorted, almost.

I added the first SR and the stepping source hung considerably, but then started.

I added the second SR and the stepping source hangs and finally comes up with an error in another component.

Usually when I've had these issues I've added resistance or a little capacitive delay where needed but so far this hasn't worked. It looks like LTSpice is confused by the initial state of the gates when the outputs are wired into inputs.

If I cut the wire with the cross it runs.

 
You can usually overcome startup ambiguities by adding an initial condition command, such as .ic v(n) = x, where n is a node of interest and x is a chosen voltage.
 
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