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Loosing hair fast - UART just won't work!!!

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Pommie

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Edit, Found the error. I had SYNC=1!!! Guess I missread the datasheet and as it was an unfamiliar chip I assumed it was something far more complicated. When you see hooves think horses not zebras.

I'm at a loss. I have a 18F26K22 on a breadboard with a RS232 to USB converter and an LED. If I short the RX and TX pins on the pic then my terminal program echoes back my key presses. I can scope the RX pin (RC7) and I see the RS232 signal on the pin. However, the pic just ignores it. I'm hoping that I've missed something stupid and so, here is the code at it's bare minimum.
C:
#include <xc.h>
#include "Config.c"

unsigned char temp;
      
int main() {
    ANSELC=0;               //all digital
    OSCCON=0x70;            //16MHz
    PLLEN=1;                //64MHz
    //setup timer 2 for 1mS interrupts
    T2CON=0x4b;             //postscaler 10, pre = 16
    PR2=99;                 //16,000,000/16/100/10 = 1000 = 1mS
    TMR2ON=1;
    //setup RS232 at 9600 baud
    //SYNC=1 BRG16=1 SPBRGx=1666 (0x682)
    TXSTA1=0b00110100;
    RCSTA1=0b10010000;
    BAUDCON1=0b00001000;    //brg16=1
    SPBRGH1=0x06;
    SPBRG1=0x82;            //9600 baud
    TRISB5=0;
    while(1){
        if(temp++>250){     //flash LED at 1 Hz
            temp=0;
            LATB5=!LATB5;
        }
        while(!TMR2IF);     //wait 2mS
        TMR2IF=0;
        while(!TMR2IF);
        TMR2IF=0;
        TXREG1=0x55;        //send every 2mS
        if(RC1IF) 
            temp=RCREG1;    //breakpoint on this line never breaks
    }
}
The LED flashes as it should but the line temp=RCREG1 is never executed and nothing appears on the TX pin.

Just in case, the config code,
C:
#include <xc.h>

// CONFIG1H
#pragma config FOSC = INTIO67   // Oscillator Selection bits (Internal oscillator block)
#pragma config PLLCFG = ON      // 4X PLL Enable (Oscillator multiplied by 4)
#pragma config PRICLKEN = ON    // Primary clock enable bit (Primary clock enabled)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRTEN = OFF     // Power-up Timer Enable bit (Power up timer disabled)
#pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

// CONFIG2H
#pragma config WDTEN = ON       // Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect)
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
#pragma config CCP3MX = PORTB5  // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
#pragma config HFOFST = ON      // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTB5   // ECCP2 B output mux bit (P2B is on RB5)
#pragma config MCLRE = EXTMCLR  // MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
Mike.
 
Last edited:

Pommie

Well-Known Member
Most Helpful Member
Just swapped the chip for a pin compatible 18F23K20 and the result is the same. What am I missing here?

Mike.
 

Pommie

Well-Known Member
Most Helpful Member
Found the error. I had SYNC=1!!! Guess I missread the datasheet and as it was an unfamiliar chip I assumed it was something far more complicated. When you see hooves think horses not zebras.

Mike.
 
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