If the digital output (LVCMOS 3V3) is heavily loaded , we may need to use buffer to meet Vih & Ioh (output high current) level of the receiver circuit.
I prefer not use the stand-alone Buffer IC's . Can anyone guide me to design my own buffer circuit based on Transistors ??
If voltage loss is an issue, couldn't you just replace the BJTs in crustchow's circuit with the corresponding MOSFETs?
You could also take a FET version of crustchow's circuit, except reverse so the P-device on the high-side and the N-device is on the low side (basically making an inverter) and then cascade two of them. Four transistors seems a little decadent, but that might just be the price you pay for going with discretes.
According to this: **broken link removed**
Losing 0.6V on the logic low could be problematic.
This may be a good solution with a 5V rail. But using 3.3V, the fet may not have an adequate Vgs threshold voltage to throw the mosfet into saturation. I did a little simulation of this with a 2n7002, single side only, and the Vds drop was worse than the equivalent Vce drop for a transistor.
This may be a good solution with a 5V rail. But using 3.3V, the fet may not have an adequate Vgs threshold voltage to throw the mosfet into saturation. I did a little simulation of this with a 2n7002, single side only, and the Vds drop was worse than the equivalent Vce drop for a transistor.