LDO Simulation of PSRR, Slew Rate,

[Gopal Adhikari]

Dear all,

I have designed a CMOS LDO with specifications
ILoad=50mA
Vdropout=200mV
the design was simulated using LTSpice IV
I just did the transient analysis and found the output voltage is good as expected.
My problem is,
I dont know how to simulate the PSRR values, the Slew rate, and what other specifications should be checked for fully analyze a LDO.
Also if possible please teach me what does PSRR give ?
If anybody knows this thing, please help me. If possible I request this gentleman to state the procedure and upload the simulated graph.

 

[spec]

In this case Power Supply Rejection Ratio (PSSR) would be a measure of the voltage noise on the input of the Low Drop Out (LDO) voltage regulator and the subsequent voltage noise that gets through the regulator and appears on the output of the regulator, normally expressed as decibels, calculated from the ratio of, Vin noise/Vout noise and ignoring impedance.

Naturally, the conditions under which you make the measurements affect the PSRR figure: circuit configuration, noise frequency, noise amplitude etc. So theses conditions must be stated to qualify the PSRR figure that you derive. Failure to do this will render any PSRR figure worthless.

For a voltage regulator, the PSRR with a saw-tooth voltage waveform in the range 50Hz to 120Hz would be fundamentally most important but so would frequencies extending from DC to 10MHz say.

Note that a simulated PSSR is unlikely to give a figure that related to an actual circuit.

spec

 

[Gopal Adhikari]

In this case Power Supply Rejection Ratio (PSSR) would be a measure of the voltage noise on the input of the Low Drop Out (LDO) voltage regulator and the subsequent voltage noise that gets through the regulator and appears on the output of the regulator, normally expressed as decibels, calculated from the ratio of, Vin noise/Vout noise and ignoring impedance.

Naturally, the conditions under which you make the measurements affect the PSRR figure: circuit configuration, noise frequency, noise amplitude etc. So theses conditions must be stated to qualify the PSRR figure that you derive. Failure to do this will render any PSRR figure worthless.

For a voltage regulator, the PSRR with a saw-tooth voltage waveform in the range 50Hz to 120Hz would be fundamentally most important but so would frequencies extending from DC to 10MHz say.

Note that a simulated PSSR is unlikely to give a figure that related to an actual circuit.

spec

thanks for the reply spec. But can you provide the circuit diagram and procedure to measure or simulate these parameters? it would help me a lot.

 

[spec]

No probs Gopal.

A simple procedure would be:
(1) Set up the regulator with 5V out put voltage
(2) Connect a 20 Ohm resistor between the LDO output and 0V to to draw 25mA
(3) Connect a 9V DC source to the input of the LDO via a 50 Ohm resistor
(4) Inject the test signal on the regulator input and monitor the resulting voltage signal on the regulator output.

spec

 

[MikeMl]

Except that most Linear regulators will not tolerate upstream resistance without a hefty bypass capacitor right across the input terminals of the regulator without breaking into oscillation. Inserting 50Ω in-line without the downstream bypass cap could cause the regulator to oscillate, making it difficult measure the PSRR. Even if it doesn't oscillate, inserting 50Ω upstream of the regulator will greatly modify the dynamic response of the regulator to a transient input disturbance...

The signal source used to inject the ripple at the regulator input will have to have a very low output impedance (i.e. be nearly an ideal voltage source) so that it simultaneously varies the input voltage to the regulator and yet provides the same low effective source resistance as the required bypass cap would.

Alternatively, leave the bypass capacitor in place, and use an upstream signal generator with a normal 50Ω output impedance to create a varying input voltage to the regulator. This obviously creates a RC low-pass filter at the input of the regulator, but that is how the regulator has to be used, anyway...

 

[spec]

Except that the stimulating device has a zero output impedance being a voltage source.

spec

 

[MikeMl]

Except that the stimulating device has a zero output impedance being a voltage source.

You are always on my case about simulation not reflecting reality.

 

[spec]

You are always on my case about simulation not reflecting reality.

I'm never on anybody's case Mike. I only deal in technical matters.

spec

 

[MikeMl]

Gopal Adhikari:
Here is your circuit, a bit cleaned up. Please check it, and make sure I didn't screw it up. Note I labeled its interface to the outside world. I am assuming you do not have a reference, and it must be external. I am assuming that your feedback resistor divider is external.

I created a symbol for it, to make the testing easier.

Now it is simple to test to see if it regulates. The choice of the feedback divider, and the reference voltage source is arbitrary, you are welcome to change them... Here is a DC sweep of just V(in) to see what happens at V(out). You can call it an LDO, because V(in) has to be only a bit more than V(out) just as it begins "regulating". Note that with the values I chose for the feedback divider and Vref, it creates a 4.8V LDO regulator.

Now, let us learn about its transient behavior as a function of changing load: Here I switch the output load from 5mA to 50mA and back again. Uh Oh! It goes unstable at high load, and it is marginally stable as the load decreases (because the oscillation is dying out...):

So it looks to me that you have some more work to do before we even get to the PSRR question. I tried different values of C1, and all that changes is the frequency at which it oscillates... Nothing new here, it is difficult to drive highly capacitive loads, regardless if C1 is part of the load, or if it is supposed to be a "bypass"

Hope I showed you some new insights into LTSpice...

 

[Gopal Adhikari]

Gopal Adhikari:
Here is your circuit, a bit cleaned up. Please check it, and make sure I didn't screw it up. Note I labeled its interface to the outside world. I am assuming you do not have a reference, and it must be external. I am assuming that your feedback resistor divider is external.simple to test to see if it regulates. .

wow! thanks MikeMI, you taught me a great deal. I cannot tell how thankful I am. I wished to get this sorts of replies.
Thank you very much.