jenniferkpj
New Member
Hi everyone! I have been struggling with the timing issue of my PIC for a few weeks and still have no success. If anyone could please help me out I would greatly appreciate it. The demo is tomorrow and I am pretty disappointed...
I have read and tried to use timer0, timer1, and timer2 to set up some clocks that my DAC needs(not in the following codes). The problem is, I need to load DATA to the DAC as well. Every time I tried to load the DATA on the line all the clocks slow down. I need decently fast clocks (for speech), and aiming for the max clock to be at least 1MHz. I am using a 40MHz crystal. Loading the DATA also causes my clocks to have weird periods...(some pulses are longer than the others).
The three clocks I need have the following relationship:
System clock = 128*fs, Back clock = 32*fs, and Leftright clock = fs, where I am using fs = 8kHz. I am using PCM 1770 from TI and PIC18F.
Here's my codes:
Thank you so much.
I have read and tried to use timer0, timer1, and timer2 to set up some clocks that my DAC needs(not in the following codes). The problem is, I need to load DATA to the DAC as well. Every time I tried to load the DATA on the line all the clocks slow down. I need decently fast clocks (for speech), and aiming for the max clock to be at least 1MHz. I am using a 40MHz crystal. Loading the DATA also causes my clocks to have weird periods...(some pulses are longer than the others).
The three clocks I need have the following relationship:
System clock = 128*fs, Back clock = 32*fs, and Leftright clock = fs, where I am using fs = 8kHz. I am using PCM 1770 from TI and PIC18F.
Here's my codes:
Code:
// DAC TEST PROGRAM
#include <16F877A.h>
int16 sample[2][10] = {
0x8E00,0xC200,0x8300,0x7D00,0x7E00,0x6B00,0x7400,0x8F00,0xA700,0xB500,
0x9B00,0x6E00,0x4800,0x2D00,0x4100,0x2D00,0x2A00,0x2200,0x1A00,0x2200
};
#define BCLK PIN_C7
#define DATALINE PIN_C6
#define LRCLK PIN_C5
#define SYSCLK PIN_C4
#use delay(clock = 10000000)
void output_DAC(long DAC_Data)
{
int c;
int d;
c = 0;
// Left bits
output_high(LRCLK);
for(d = 15; d != -1; d--)
{
output_bit(DATALINE, bit_test(DAC_Data, d));
for (c = 0; c < 2; c++)
{
output_high(SYSCLK);
output_low(SYSCLK);
}
output_high(BCLK);
d++;
for (c = 0; c < 2; c++)
{
output_high(SYSCLK);
output_low(SYSCLK);
}
output_low(BCLK);
}
d = 0;
output_low(LRCLK);
for(d = 15; d != -1; d--)
{
output_bit(DATALINE, bit_test(DAC_Data, d));
for (c = 0; c < 2; c++)
{
output_high(SYSCLK);
output_low(SYSCLK);
}
output_high(BCLK);
d++;
for (c = 0; c < 2; c++)
{
output_high(SYSCLK);
output_low(SYSCLK);
}
output_low(BCLK);
}
}
void DAC_Sample()
{
int c, r;
// Initial clock state
output_low(BCLK);
output_low(SYSCLK);
output_low(LRCLK);
for (c = 0; c < 250; c++)
{
for (r = 0; r < 10; r++)
output_DAC(sample[c][r]);
}
}
void main()
{
int i = 0;
int ts, tb;
int bitindex;
int colindex;
int rowindex;
long databyte;
setup_timer_0(RTCC_INTERNAL |RTCC_DIV_256 );
set_timer0(0);
setup_timer_1(T1_INTERNAL | T1_DIV_BY_1);
set_timer1(0);
databyte = sample[colindex][rowindex];
// timer interval for timer bits
tb = 0;
ts = 0;
//tempbit = temp.1;
while(1)
{
}
}
Thank you so much.
Last edited: