Hello,
The circuit on page 17 of AN1792 (R8, R9, C6, C7, D3) makes the L6562 PFC controller operate with Constant Off Time.
The power FET of the converter is switched on when the ZCD pin of L6562 (pin 5) voltage falls below 0.7V. The FET subsequently gets switched OFF when the Current sense resistor voltage breaches the sense threshold. However, the ZCD pin voltage must rise above 1.4V so that the ZCD pin is again “armed”. –But supposing that the ZCD pin has not risen above 1.4V when the current sense threshold is breached (this would happen when ON time was short). What would happen in this case.
The attached is a LTspice simulation of the Constant off time circuit. You can see that the voltage on the ZCD pin takes time to rise up above 1.4V.
AN1792 Fixed off time controlled PFC regulators:
**broken link removed**
L6562 datasheet:
https://www.st.com/resource/en/datasheet/l6562a.pdf
The circuit on page 17 of AN1792 (R8, R9, C6, C7, D3) makes the L6562 PFC controller operate with Constant Off Time.
The power FET of the converter is switched on when the ZCD pin of L6562 (pin 5) voltage falls below 0.7V. The FET subsequently gets switched OFF when the Current sense resistor voltage breaches the sense threshold. However, the ZCD pin voltage must rise above 1.4V so that the ZCD pin is again “armed”. –But supposing that the ZCD pin has not risen above 1.4V when the current sense threshold is breached (this would happen when ON time was short). What would happen in this case.
The attached is a LTspice simulation of the Constant off time circuit. You can see that the voltage on the ZCD pin takes time to rise up above 1.4V.
AN1792 Fixed off time controlled PFC regulators:
**broken link removed**
L6562 datasheet:
https://www.st.com/resource/en/datasheet/l6562a.pdf
