Is the checking of both WCOL and SSPOV registers essential for SPI?

Hi
I am trying out SPI between a pic16f72 and a MAXQ3180. I am not able to get an ack from the max . I have not used the interrupt mode. I am just communicating only in polling mode. I have checked both the WCOL and the SSPOV registers ,but I don know the reason for why the communication is not taking place.I have attached the SPI part of my code here. Please help me find out the mistake am doing....


void main()
{
ADCON1=0X07;
TRISA=0X00;
TRISB=0X00;
PORTB=0X00;
TRISC=0X10;
PORTC=0X00;
SSPCON=0b00110000;


/* // bit3-0 |||||____ SSPM<3:0>: Synchronous Serial Port Mode Select bits. 0000 = SPI Master mode, clock = FOSC/4
// bit4 * ||||_____ CKP: Clock Polarity Select bit, 1 = Idle state for clock is a high level. 0 = Idle state for clock is a low level
// bit5 |||______ SSPEN: Synchronous Serial Port Enable bit. 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins(1)
// bit6 ||_______ SSPOV: Receive Overflow Indicator bit. 0 = No overflow */
// bit7 |________ WCOL: Write Collision Detect bit. 0 = No collision

//SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (SPI Mode)



SSPSTAT=0b11000000;


/* bit7 ||||||||_ BF: Buffer Full Status bit. 0 = Receive not complete, SSPBUF is empty.
bit6 |||||||__ No use. Used in I2C mode only.
bit5 ||||||___ "
bit4 |||||____ "
bit3 ||||_____ "
bit2 |||______ "
bit1 * ||_______ CKE: SPI Clock Edge Select bit. 1 = Data stable on falling edge of SCK
bit0 * |________ SMP: SPI Data Input Sample Phase bit. SPI Master mode: 0 = Input data sampled at middle of data output time.*/
write_enable();
SPI_SS=1;
}



void write_enable()
{
unsigned char i;
unsigned char send_data[3]={0x00,0x80,0x00}; //reading data from the address 0x080 of the max
SPI_SS=0; // SLAVE SELECT-ACTIVE LOW
SPI_CLK=1; // CLOCK-ACTIVE HIGH
for(i=0;i<3;i++)
{
dummy=SPI_OUTPUT(send_data);
switch_module(SSPBUF);
}
}

void switch_module(unsigned char c)
{
switch(c)
{
case 0xc1:

delay_100uS();
break;

case 0xc2:

delay_100uS();
break;

case 0x4e:

delay_100uS();
if(WCOL) WCOL=0;
if(SSPOV) SSPOV=0;
SSPBUF=0x00;
while(!SSPIF);
SSPIF=0;
while(!BF);
BF=0;
delay_100uS();
switch_module(SSPBUF);
break;

case 0x41:

delay_100uS();
get_data_byte();
break;

default:

RB7=1;
delay_200mS();
break;
}
}

unsigned char SPI_OUTPUT(unsigned char a)
{
if(WCOL)
WCOL=0;
if(SSPOV)
SSPOV=0;
SSPBUF=a;
while(!BF);
BF=0;
// dummy=SSPBUF;
return(SSPBUF);
}

void get_data_byte()
{

if(WCOL) WCOL=0;
if(SSPOV) SSPOV=0;
SSPBUF=0x00;
while(!BF);
BF=0;
result1=SSPBUF;
if(WCOL) WCOL=0;
if(SSPOV) SSPOV=0;
SSPBUF=0x00;
while(!BF);
BF=0;
result2=SSPBUF;
PORTB=result2;
}