Is amp output of a MOSFET driver affected by switching frequency?

[strantor]

I'm looking through the data sheet of a FAN3121 Low side MOSFET driver and it specifies the the peak output @11.4A (no test conditions given) on the front page, then on page 6 it shows the peak output of 7.1A with a VDD of 6V and at a frequency of 1KHz. I am wondering if I need to derate the amps output if I plan to run 20KHz. I can't find a graph in the datasheet of A Vs. Hz. In fact there is no frequency spec anywhere in the data sheet. Does this mean it will have the same current output at any frequency? if so, why did they include it as a test condition in the spec of 7.1A?

 

[alec_t]

The gate input of a power FET has considerable capacitance (the datasheet should specify that), so the higher the input frequency the higher the drive current needed through that capacitance. This is probably a limiting factor for the FET performance.

 

[strantor]

I did see the graph of driver input current vs frequency; as frequency goes up, input current goes up, but I was more worried that as frequency goes up, output current goes down. I guess that's not the case?

 

[alec_t]

I assume (not being an expert on this) that if the FET has to handle increased gate current there will inevitably be heat generated in the package. As the package can dissipate only so much heat in total then the drain-source output current (and consequent resistive power loss) would have to be reduced to compensate or the FET would die.

 

[strantor]

I assume (not being an expert on this) that if the FET has to handle increased gate current there will inevitably be heat generated in the package. As the package can dissipate only so much heat in total then the drain-source output current (and consequent resistive power loss) would have to be reduced to compensate or the FET would die.

In the portion I bolded, are you referring to the driver package or the FET package? I was under the impression that since the FET is voltage controlled and not current controlled, and the amperage output spec of the driver is relevant only to the gate charge charging time, that no current from the gate actually flowed through the FET so no additional heat (in addition to heat generated from current flowing from drain to source) would be generated. But, I'm still not sure I understood you correctly.

The current I was referring to when asked about "as frequency goes up, current goes down" is the current output of the driver, to charge the gate capacitcance. The driver data sheet claims 11.4A output @ 1KHz; I am unsure if I will still have 11.4A output if I am switching @ 20KHz

 

[alec_t]

are you referring to the driver package or the FET package?

I meant the FET package. I misinterpreted your 'mosfet driver' as a 'mosfet which is driving something', rather than 'something which drives a mosfet'. So, scrub my earlier comments and replace with 'Sorry, don't know'.

 

[misterT]

Low side MOSFET driver and it specifies the the peak output @11.4A (no test conditions given) on the front page, then on page 6 it shows the peak output of 7.1A with a VDD of 6V and at a frequency of 1KHz.

The VDD/2 measurement is supposed to give you an idea of continuous source/sink performance. Below those numbers are also listed the peak source/sink 10.6 and 11.4 A. The test load 1uF is huge compared to what mosfet gates really have. Don't worry about switching frequency vs. output current. Output rise- and fall-times (and gate capacitance) are the ones that limit switching frequency. You can still easily do 20kHz with that driver.. even 200kHz won't be a problem with most mosfets. You need to degrade the peak output with a small resistor to avoid negative voltage transients and other problems of high-speed mosfet switching.

What is the application and what kind of mosfet you have? Maybe we can do some real calculations for you.

 

[RCinFLA]

This driver has a parallel MOSFET and bipolar for driving the output. The parallel bipolar improves low Vdd drive performance over just a MOSFET alone. The bipolar will have some drop off in drive current at higher frequency.

All MOSFET's Rds-ON will be greater with less gate voltage drive. Dropping from 12v to 6v gate drive will increase Rds-ON of MOSFET section of driver.

You need to be sure of the gate switching voltage requirements of the MOSFET you want to drive. Most high power MOSFET need at least 10 volts gate drive to achieve low Rds-ON. If you are using a 12v supply you will not have driver current dropoff with switching frequency as the driver will be MOSFET driver dominated for the output current. What the 11.4 amps at 12v supply means its Nch device in the driver will have an Rds-ON of about 1 ohm with the 12v supply swing. The Pch pull up will have a greater Rds-ON and less pullup drive current at any supply but again it will be comparitive lower at higher supply voltage.

 

[strantor]

The VDD/2 measurement is supposed to give you an idea of continuous source/sink performance. Below those numbers are also listed the peak source/sink 10.6 and 11.4 A. The test load 1uF is huge compared to what mosfet gates really have. Don't worry about switching frequency vs. output current. Output rise- and fall-times (and gate capacitance) are the ones that limit switching frequency. You can still easily do 20kHz with that driver.. even 200kHz won't be a problem with most mosfets. You need to degrade the peak output with a small resistor to avoid negative voltage transients and other problems of high-speed mosfet switching.

What is the application and what kind of mosfet you have? Maybe we can do some real calculations for you.

Its a IRFP4110PbF. I had planned to max our the VDD @ 18V so that I can use a 1.5Ω resistor and still get the full 11.4A out of it. do you think that is enough to prevent ringing?

 

[misterT]

Its a IRFP4110PbF. I had planned to max our the VDD @ 18V so that I can use a 1.5Ω resistor and still get the full 11.4A out of it. do you think that is enough to prevent ringing?

The optimum gate resistor depends on the parasitic inductance in the gate charging circuit. So it is very difficult to say any values. Add some resistance to get damping (~5 ohms). You can put a diode in parallel with the resistor to get faster turn-off time. Keep the driver IC close to the mosfet and use good bypass capacitors for the driver IC supply pins.

I realized that it is very difficult to do usefull calculations without knowing the application in detail. If you are willing to learn this stuff, here is some good reading material:
https://www.electro-tech-online.com/custompdfs/2011/09/slup169.pdf

If you really want to tune the performance, you need to build a prototype and do some measurements and then redesign etc..

 

[strantor]

The optimum gate resistor depends on the parasitic inductance in the gate charging circuit. So it is very difficult to say any values. Add some resistance to get damping (~5 ohms). You can put a diode in parallel with the resistor to get faster turn-off time. Keep the driver IC close to the mosfet and use good bypass capacitors for the driver IC supply pins.

I realized that it is very difficult to do usefull calculations without knowing the application in detail. If you are willing to learn this stuff, here is some good reading material:
https://www.electro-tech-online.com/custompdfs/2011/09/slup169-1.pdf

If you really want to tune the performance, you need to build a prototype and do some measurements and then redesign etc..

Yes I have printed that paper out, just need to read it. .
I never thought about the diode; that's a good idea, so I don't limit my current going in, but I do limit it going in. And what you said about the inductance being specific to the design, I am finding that out also. I'm trying to strike a balance between just buying a bunch of parts and blowing them up/ and reading everything there is to read about circuit design and MOSFETs. Every time I think I'm ready, I get another curve ball. The latest curve ball was the linear derating factor; I'm in the middle of going back to the beginning.